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smartrf ? CC2420 CC2420 2.4 ghz ieee 802.15.4 / zigbee rf transceiver applications ? 2.4 ghz ieee 802.15.4 system s ? zigb ee syst em s ? consum er electronics ? industrial control ? hom e /building autom ation ? pc peripherals product description the CC2420 is a true single-chip 2.4 ghz ieee 802.15.4 compliant rf transceiver designed for low-power and low-voltage wireless applications. CC2420 includes a digital direct sequence spread spectrum baseband modem providing a spreading gain of 9 db and an effective datarate of 250 kbps. the CC2420 is a low-cost, highly integrated solution for robust wireless communication in the 2.4 ghz unlicensed ism band. it complies with world-wide regulations covered by en 300 440 (europe), cfr47 part 15 (us) and arib std-t-66 (japan). the CC2420 provides extensive hardware support for packet handling, data buffering, burst transmissions, data encryption, data aut hentication, clear channel assessment, link quality indication and packet timing information. these features reduce the load on the host controller and allow CC2420 to interfac e low-cost microcont rollers. the configuration interface and transmit / receive fifos of CC2420 are accessed via a spi interface. in a typical application CC2420 will be used together with a microcontroller and a few external passive components. CC2420 is based on chipcon?s smartrf ? - 03 technology in 0.18 m cmos. key features ? true s i ngle-c h ip 2.4 ghz ieee 802.15.4 compliant rf transceiver with baseband modem and mac support ? dsss baseband modem with 2 mchips/s and 250 kbps effective data rate. ? suitable for both rfd and ffd operation ? low current consumption (rx: 19.7 ma, tx: 17.4 ma) ? low supply voltage (2.1 ? 3.6 v) with integrated voltage regulator ? low supply voltage (1.6 ? 2.0 v) with external voltage regulator ? programmable output power ? no external rf switch / filter needed ? i/q low-if rec e iver ? i/q direct upconversion transmitter ? very few external components ? 128 (rx) + 128 (tx) byte data buffering ? digital rssi / lqi support ? hardware mac encryption (aes-128) ? battery monitor ? qlp-48 package, 7x7 mm ? complies with en 300 440 and fcc cfr-47 part 15, arib std-t-66 ? powerful and flexible development tools available this document contains information on a pre-production product. spec ifications and informati on herein are subject to change w i thout notice. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 1 of 85
smartrf ? CC2420 table of contents abbrevi a ti ons _____________________________________________________________________ 4 referen ces _______________________________________________________________________ 5 featu res _________________________________________________________________________ 6 absol u te maxi mu m rati ngs _________________________________________________________ 7 e l ectri cal speci fi cati ons ____________________________________________________________ 8 pi n assi gn ment __________________________________________________________________ 13 ci rcui t des cri pti o n _______________________________________________________________ 15 appl i c ati o n ci rcui t _______________________________________________________________ 17 input / out put m a t c hi ng ___________________________________________________________ 17 b i as resi st or ____________________________________________________________________ 17 c r y s t a l ________________________________________________________________________ 17 vol t a ge regul at or ________________________________________________________________ 17 power supply decoupli ng and filte ring _______________________________________________ 17 ieee 802.15.4 modulat ion format __________________________________________________ 21 confi g urati o n overvi e w ___________________________________________________________ 22 e val uati on softw are ______________________________________________________________ 22 4-w i re seri al confi g urati o n and data interface ________________________________________ 23 register access _________________________________________________________________ 23 st at us by t e _____________________________________________________________________ 24 c o m m a nd st robes _______________________________________________________________ 25 ram acces s ____________________________________________________________________ 25 fifo acces s ____________________________________________________________________ 27 multiple spi access ______________________________________________________________ 27 mi crocontrol l er interface and pi n des cri pti o n ________________________________________ 28 c onfi gurat i on i n t e rface ___________________________________________________________ 28 receive m ode __________________________________________________________________ 29 r x fifo overfl ow _______________________________________________________________ 29 transm i t m ode __________________________________________________________________ 30 general cont rol a nd st at us pi ns _____________________________________________________ 30 demodul ator, symbol synchron i s er and data deci si on _________________________________ 31 frame fo rmat ___________________________________________________________________ 31 sy nchroni sat i on header ___________________________________________________________ 32 lengt h fi el d ____________________________________________________________________ 33 m a c prot ocol dat a uni t ___________________________________________________________ 33 fram e check sequence ____________________________________________________________ 33 rf data b u fferi ng ________________________________________________________________ 34 b u ffered t r ansm i t m ode ___________________________________________________________ 35 buffered recei ve m ode ___________________________________________________________ 35 un-buffered, se ri al m ode __________________________________________________________ 35 address rec ogni t i o n ______________________________________________________________ 36 acknow l edge frames _____________________________________________________________ 37 radi o control st ate machi n e ________________________________________________________ 39 mac securi ty operati ons (e ncry pti o n and authen ti cati on) _____________________________ 41 key s __________________________________________________________________________ 41 chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 2 of 85
smartrf ? CC2420 nonce / count er _________________________________________________________________ 41 st and-al one en cry p t i o n ___________________________________________________________ 42 in-l i n e securi t y operat i ons _________________________________________________________ 42 c t r m ode encry p t i on / decry p t i o n __________________________________________________ 43 cbc-mac _____________________________________________________________________ 43 c c m _________________________________________________________________________ 43 ti m i ng ________________________________________________________________________ 44 l i near if and agc setti ngs ________________________________________________________ 45 rssi / e n ergy detecti o n ___________________________________________________________ 45 link quality indication ___________________________________________________________ 46 cl ear channel assessmen t _________________________________________________________ 46 frequency and cha nnel progra mmi ng _______________________________________________ 47 vco and pl l sel f-cal i b rati on _____________________________________________________ 47 vc o _________________________________________________________________________ 47 pll sel f-ca l i b rat i o n ______________________________________________________________ 47 output pow er programmi ng _______________________________________________________ 48 vol t age regul a tor ________________________________________________________________ 49 b a ttery moni tor __________________________________________________________________ 49 crystal osc illator ________________________________________________________________ 51 input / output matching __________________________________________________________ 52 t r ansmi tter t e st modes ___________________________________________________________ 52 unm odul at ed carri er _____________________________________________________________ 52 m odul at ed spect rum _____________________________________________________________ 53 system consi d erati ons and gui d el i n es _______________________________________________ 55 frequency hopping and m u lti- channel sy stem s _________________________________________ 55 dat a burst t r ansm i ssi ons __________________________________________________________ 55 crystal accuracy and drift _________________________________________________________ 55 c o m m uni cat i on robust n ess ________________________________________________________ 55 c o m m uni cat i on securi t y __________________________________________________________ 55 low cost sy st em s ________________________________________________________________ 56 b a t t e ry operat e d sy st em s __________________________________________________________ 56 b e r / per m eas urem ent s _________________________________________________________ 56 pcb layout reco mmendation s _____________________________________________________ 57 antenna consi d erati ons ___________________________________________________________ 57 confi g urati o n regi sters ___________________________________________________________ 59 t e st output si gnal s _______________________________________________________________ 79 package descri pt i o n (ql p 48) ______________________________________________________ 81 package t h erm a l propert i e s ________________________________________________________ 82 sol d eri ng i n form at i o n ____________________________________________________________ 82 pl ast i c t ube sp eci fi cat i o n __________________________________________________________ 82 c a rri er t a pe and r eel speci fi cat i o n ___________________________________________________ 82 orderi ng in formati on _____________________________________________________________ 83 general info rmati on ______________________________________________________________ 84 address info rmati on ______________________________________________________________ 85 chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 3 of 85
smartrf ? CC2420 abbreviations adc - analog to digital converter aes - advanced encryption standard agc - automatic gain control arib - association of radio industries and businesses ber - bit error rate cbc-mac - cipher block chaini ng message authentication code cca - clear cannel assessment ccm - counter mode + cbc-mac cfr - code of federal regulations ctr - counter mode (encryption) cw - continuous wave dac - digital to analog converter dsss - direct sequence spread spectrum esd - electro static discharge esr - equivalent series resistance evm - error vector magnitude fcc - federal communications commission fcf - frame control field fifo - firs t in firs t out ffctrl - fifo and frame control hssd - high speed serial debug ieee - institute of electrical and electronics engineers if - intermediate frequency ism - industrial, scientific and medical itu-t - international telecommunication union ? telecommunication standardization sector i/o - input / output i/q - in-phase / quadrature-phase kbps - kilo bits per second lna - low-noise amplifier lo - local oscillator lqi - link quality indication lsb - least significant bit / byte mac - medium access control mfr - mac footer mhr - mac header mic - message integrity code mpdu - mac protocol data unit msdu - mac serv ice data unit na - not available nc - not connected o-qpsk - offset - quadrature phase shift keying pa - power amplifier pcb - printed circuit board per - packet error rate phy - physical layer phr - phy header pll - phase locked loop psdu - phy servic e data unit qlp - quad leadless package ram - random access memory rbw - resolution bandwidth rf - radio frequency rssi - receive signal strength indicator rx - receiv e chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 4 of 85
smartrf ? CC2420 shr - synchronisation header spi - serial peripheral interface tbd - to be decided / to be defined t/r - transmit / receive tx - transmit vco - voltage controlled oscillator vga - variable gain amplifier references [1] ieee std. 802.15.4/d18 - 2003: wire lesss medium access control (mac) and physical layer (phy) specificati ons for low rate wireless personal area networks (lr-wpans) http://www.ieee802.org/15/pub/tg4.html [2] nist fips pub 197: advanced encryption standard (aes), federal information processing standards p ublication 197, us department of commerce/n.i.s.t., november 20014. ava ilable from the nist website. http://csrc.nist.gov/publicat ions/fips/fips197/fips-197.pdf [3] r. housley, d. whiting, n. fe rguson, counter with cbc-mac (ccm), submitted to nist, june 3, 2002. av ailable from the nist website. http://csrc.nist.gov/publicat ions/fips/fips197/fips-197.pdf chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 5 of 85
smartrf ? CC2420 features ? 2400 ? 2483.5 mhz rf transceiver ? direct sequence spread spec trum (dsss) trans c e iver ? 250 kbps data rate, 2 mchip/s c h ip rate ? o-qpsk with half s i ne puls e shaping modulation ? very low current consumption (rx: 19.7 ma, tx: 17.4 ma) ? high sensitivity (-94 dbm) ? high adjacent channel rejection (39 db) ? high alternate channel rejection (46 db) ? on-chip vco, lna and pa ? low supply voltage (2.1 ? 3.6 v) with on-chip voltage regulator ? programmable output power ? i/q low-if s o ft dec is ion rec e iver ? i/q direct up-conversion trans mitter ? separate transmit and receive fifos ? 128 byte transmit data fifo ? 128 byte receive data fifo ? very few external components ? only reference crystal and a minimised number of passives ? no external filters needed ? easy configuration interface ? 4-wire spi interface ? serial clock up to 10 mhz ? 802.15.4 mac hardware support: ? automatic preamble generator ? synchronisation word insertion/detection ? crc-16 computation and checking over the mac payload ? clear channel assessment ? energy detection / digital rssi ? link quality indication ? full automatic mac security (ctr, cbc-mac, ccm) ? 802.15.4 mac hardware security: ? automated security operations within the receive and transmit fifos. ? ctr mode encryption / decryption ? cbc-mac authentication ? ccm encryption / decryption and authentication ? stand-alone aes encryption ? development tools available ? fully equipped development kit ? demonstration board reference design with microcontroller code ? easy-to-use software for generating the CC2420 configu- ration data ? small size qlp-48 package, 7 x 7 mm ? complies with en 300 440 and fcc cfr47 part 15, arib std-t-66 chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 6 of 85
smartrf ? CC2420 absolute maximum ratings parameter min. max. units condition supply voltage, chip core, avdd/dvdd1.8 ? 0 . 3 2 . 0 v voltage on any pin, core ? 0 . 3 v d d + 0 . 3 , max 2.0 v voltage on any pin, digital i/o (pin no. 21, 27-34 and 41) - 0 . 3 v d d i o + 0 . 3 , max 3.6 v input rf level 10 dbm storage temperature range ? 5 0 1 5 0 c lead temperature 260 c t = 10 s the absolute maximum ratings given above should under no circumstances be violated. stress exceeding one or more of the limiting values may cause permanent damage to the device. caution! esd sensitive device. precaution should be used when handling the device in order to prevent perm anent dam age. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 7 of 85
smartrf ? CC2420 electrical specifications tc = 27 c, dvdd3.3 and vreg_in = 3.0v, internal voltage regulator used if nothing else stated parameter min. ty p. max. unit condition / note ov e r a l l operating ambient temperature range ? 4 0 8 5 c rf frequency range 2400 2483.5 mhz programmable in 1 mhz steps, 5 mhz steps for compliance w i th [1] transmit section transmit bit rate 250 250 kbps as defined by [1] transmit chip rate 2000 2000 kchips/s as defined by [1] nominal output pow er -3 0 dbm delivered to a single ended 50 ? load through a balun. [1] requires minimum ?3 dbm programmable output pow er range 4 0 d b the output pow er is programmable in 8 steps from approximately ?24 to 0 dbm. harmonics 2 nd harmonic 3 rd harmonic -34 -60 dbc dbc at max output pow er delivered to a single ended 50 ? load through a balun. see page 52. spurious emission 30 - 1000 mhz 1? 12.75 ghz 1.8 ? 1.9 ghz 5.15 ? 5.3 ghz -36 -30 -47 -47 dbm dbm dbm dbm maximum output pow er. complies w i th en 300 440, cfr47, part 15 and arib std- t-66 error vector magnitude (evm) 20 % measured as defined by [1] [1] requires max. 35 % optimum load impedance 115 + j180 ? differential impedance as seen from the rf-port ( rf_p and rf_n ) tow a rds the antenna. for matching details see the input / output matching section on page 52. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 8 of 85
smartrf ? CC2420 parameter min. ty p. max. unit condition / note receiv e section receiver sensitivity -90 -94 dbm per = 1%, as specified by [1] measured in 50 ? single ended through a balun. [1] requires ?85 dbm saturation (maximum input level) 0 10 dbm per = 1%, as specified by [1] measured in 50 ? single ended through a balun. [1] requires ?20 dbm adjacent channel rejection + 5 mhz channel spacing 39 db wanted signal @ -82 dbm, adjacent modulated channel at 5 mhz, per = 1 %, as specified by [1]. [1] requires 0 db adjacent channel rejection - 5 mhz channel spacing 46 db wanted signal @ -82 dbm, adjacent modulated channel at 5 mhz, per = 1 %, as specified by [1]. [1] requires 0 db alternate channel rejection + 10 mhz channel spacing 53 db wanted signal @ -82 dbm, adjacent modulated channel at 10 mhz, per = 1 %, as specified by [1] [1] requires 30 db alternate channel rejection - 10 mhz channel spacing 57 db wanted signal @ -82 dbm, adjacent modulated channel at 10 mhz, per = 1 %, as specified by [1] [1] requires 30 db blocking / desensitisation* 30 - 2000 mhz 2000 - 2399 mhz 2498 - 3000 mhz 3 ? 12.75 ghz (*out-of-band spurious response r e jection) -10 -27 -27 -10 dbm dbm dbm dbm wanted signal 3 db above the sensitivity level, cw jammer , per = 1%. in-band spurious reception 39 db ratio betw een sensitivity for an unw anted frequency to the sensitivity in the w anted channel. the signal source is a 802.15.4 modulated channel, sw ept over all channels from 2405 to 2480 mhz. signal level for per = 1% adjacent channels and image channel are excluded. lo leakage ? 4 7 d b m chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 9 of 85
smartrf ? CC2420 parameter min. ty p. max. unit condition / note spurious emission 30 ? 1 ghz 1 ? 12.75 ghz ? 57 ? 47 dbm dbm complies w i th en 300 440, cfr47, part 15 and arib std- t-66 frequency error tolerance -300 300 khz difference betw een center frequency of the received rf signal and local oscillator frequency [1] requires 200 khz sy mbol rate error tolerance 120 ppm difference betw een incoming sy mbol rate and the internally generated sy mbol rate [1] requires 80 ppm rssi / carrier sense carrier sense level ? 77 dbm programmable in rssi.cca_thr rssi dy namic range 100 db the range is approximately from ?100 dbm to 0 dbm rssi accur a cy 6 d b see page 45 for details rssi linearity 3 d b rssi average time 128 s 8 sy mbol periods, as specified by [1] if section intermediate frequency (if) 2 mhz frequency sy nthesiz e r section cry s tal oscillator frequency 16 mhz see page 51 for details. cry s tal frequency accuracy requirement - 40 40 ppm including aging and temperature dependency , as specified by [1] cry s tal operation p a r a l l e l c4 and c5 are loading capacitors, see page 51 cry s tal load capacitance 1 2 1 6 2 0 p f 16 pf recommended cry s tal esr 6 0 ? cr y s tal oscillator star t- up time 0.86 ms 16 pf load chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 10 of 85
smartrf ? CC2420 parameter min. ty p. max. unit condition / note phase noise ? 109 ? 117 ? 117 ? 117 dbc/hz dbc/hz dbc/hz dbc/hz unmodulated carrier at 1 mhz offset from carrier at 2 mhz offset from carrier at 3 mhz offset from carrier at 5 mhz offset from carrier pll loop bandw idth 50 khz pll lock time (rx / tx turnaround time) 1 9 2 s digital inputs/outputs signal levels are referred to the voltage level at the pin dvdd3.3 logic "0" input voltage 0 0 . 3 * dvdd v logic "1" input voltage 0.7* dvdd d v d d v logic "0" output voltage 0 0 . 4 v output c u r r e n t ? 8 ma, 3.3 v supply voltage logic "1" output voltage 2.5 vdd v output current 8 ma, 3.3 v supply voltage logic "0" input current n a ? 1 a input signal equals gnd logic "1" input current n a 1 a input signal equals vdd fifo setup time 20 ns tx un-buffered mode, minimum time fifo must be ready before the positive edge of fifop fifo hold time 10 ns tx un-buffered mode, minimum time fifo must be held after the positive edge of fifop serial interface pins ( sclk , si , so and csn ) timing specification see table 4 on page 24 voltage regulator input voltage 2 . 1 3 . 0 3 . 6 v on the vreg_in pin output voltage 1 . 7 1 . 8 1 . 9 v on the vreg_out pin quiescent current 1 3 2 0 2 9 a no current draw n from the vreg_out pin. min and max numbers include 2.1 through 3.6 v input voltage startup time 0 . 3 0 . 6 m s chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 11 of 85
smartrf ? CC2420 parameter min. ty p. max. unit condition / note battery monitor current consumption 6 3 0 9 0 a when enabled startup time 1 0 0 s voltage regulator already enabled settling time 2 s new toggle voltage programmed step size 5 0 m v hy steresis 1 0 m v absolute accur a cy 10 % may be softw are calibrated for know n reference voltage relative accur a cy t b d % pow e r supply recommended operation voltage rf and analog digital core digital i/o 1.8 1.8 3.0 v v v regulated 1.8 v supply voltage generated by on-chip voltage regulator. supply voltage, operating limits rf and analog digital core digital i/o voltage regulator input 1.6 1.6 1.6 2.1 2.0 2.0 3.6 3.6 v v v regulated 1.8 v supply voltage generated by on-chip voltage regulator. the digital i/o voltage ( dvdd3.3 pin) must match the external interfacing circuit (e.g. microcontroller). current consumption in different modes (see figure 23, page 40) pow e r dow n mode (off) idle mode (idle) cr y s tal oscillator on ( x o s c_o n ) 20 365 1 a a a current draw n from vreg_in , through voltage regulator voltage regulator off voltage regulator on including voltage regulator current consumption, receive mode 1 9 . 7 m a current consumption, transmit mode: p = -25 dbm p = -15 dbm p = -10 dbm p = ? 5 dbm p = 0 dbm 8.5 9.9 11 14 17.4 ma ma ma ma ma the output pow er is delivered differentially to a 50 ? singled ended load through a balun, see also page 52. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 12 of 85
smartrf ? CC2420 pin assignment vr e g _ o u t a v dd_ chp qlp48 7x7 1 2 3 4 5 6 7 8 9 10 11 12 35 34 33 32 31 30 29 28 27 26 25 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 CC2420 r_bias a v dd_ if1 vr e g _ i n vr e g _ e n x o sc 16_q1 x o sc 16_q2 a t est2 a t est1 nc rf_ p rf_ n avd d _ pr e a v dd_ rf1 tx r x _ s w i tc h avd d _ vc o v c o_guard avd d _ sw gnd gnd nc nc ds ub _ c ore ds ub _ p a d s avd d _ ad c dv dd_ a d c dgua rd a v dd_ if2 dgnd_ gua r d a v dd_ rf2 dgnd nc cs n fifo fifop cca sfd dv dd1 .8 sc lk dv dd_ ra m si so dv dd3 .3 nc a v d d _ xosc 16 nc agn d ex posed di e attach pad r esetn figure 1. CC2420 pinout ? top view pin pin name pin ty pe pin description - agnd ground (analog) exposed die attach pad. must be connected to solid ground plane 1 vco_guard pow e r (analog) connection of guard ring for vco (to avdd) shielding 2 avdd_vco pow e r (analog) 1.8 v pow e r supply for vco 3 avdd_pre pow e r (analog) 1.8 v pow e r supply for prescaler 4 avdd_rf1 pow e r (analog) 1.8 v pow e r supply for rf front-end 5 gnd ground (analog) grounded pin for rf shielding 6 rf_p rf i/o positive rf input/output signal to lna/from pa in receive/transmit mode 7 txrx_switch pow e r (analog) common supply connection for integrated rf front-end. must be connected to rf_p and rf_n externally through a dc path 8 rf_n rf i/o negative rf input/output signal to lna/from pa in receive/transmit mode 9 gnd ground (analog) grounded pin for rf shielding 10 avdd_sw pow e r (analog) 1.8 v pow e r supply for lna / pa sw itch 11 nc - n o t c o n n e c t 12 nc - n o t c o n n e c t 13 nc - n o t c o n n e c t chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 13 of 85
smartrf ? CC2420 pin pin name pin ty pe pin description 14 avdd_rf2 pow e r (analog) 1.8 v pow e r supply for receive and transmit mixers 15 avdd_if2 pow e r (analog) 1.8 v pow e r supply for transmit / receive if chain 16 nc - n o t c o n n e c t 17 avdd_adc pow e r (analog) 1.8 v pow e r supply for analog parts of adcs and dacs 18 dvdd_adc pow e r (digital) 1.8 v pow e r supply fo r digital parts of receive adcs 19 dgnd_guard ground (digital) ground connection fo r digital noise isolation 20 dguard pow e r (digital) 1.8 v pow e r supply c onnection for digital noise isolation 21 resetn digital input asy n chronous, active low digital reset 22 dgnd ground (digital) ground connection for digital core and pads 23 dsub_pads ground (digital) substrate connection for digital pads 24 dsub_core ground (digital) substrate c onnection for digital modules 25 dvdd3.3 pow e r (digital) 3.3 v pow e r supply for digital i/os 26 dvdd1.8 pow e r (digital) 1.8 v pow e r supply for digital core 27 sfd digital output sfd (start of frame delimiter) / digital mux output 28 cca digital output cca (clear channel assessment) / digital mux output 29 fifop digital output high w hen number of by tes in fifo exceeds threshold / serial rf clock output in test mode 30 fifo digital i/o high w hen data in fifo / serial rf data input / output in test mode 31 csn digital input spi chip select, active low 32 sclk digital input spi clock input, up to 10 mhz 33 si digital input spi slave input. sa mpled on the positive edge of sclk 34 so digital output (tristate / pullup) spi slave output. updated on the negative edge of sclk. tristate w hen csn high. programmable internal pullup 35 dvdd_ram pow e r (digital) 1.8 v pow e r supply for digital ram 36 nc - n o t c o n n e c t 37 avdd_xosc16 pow e r (analog) 1.8 v cry s tal oscillator pow er supply 38 xosc16_q2 analog i/o 16 mhz cr y s tal oscillator pin 2 39 xosc16_q1 analog i/o 16 mhz cry s tal oscillator pin 1 or ex ternal clock input 40 nc - n o t c o n n e c t 41 vreg_en digital input voltage regulator enable, active high, held at vreg_in voltage level w hen active 42 vreg_out pow e r output voltage regulator 1.8 v pow er supply output 43 vreg_in pow e r (analog) voltage regulator 2.1 to 3.6 v pow er supply input 44 avdd_if1 pow e r (analog) 1.8 v pow e r supply for transmit / receive if chain 45 r_bias analog output external precision resistor, 43 k ? , 1 % 46 atest2 analog i/o analog test i/o for prototy pe and production testing 47 atest1 analog i/o analog test i/o for prototy pe and production testing 48 avdd_chp pow e r (analog) 1.8 v pow e r suppl y for phase detector and charge pump no tes: the exposed die attach pad must be connected to solid ground plane as this is the main ground connection for the chip. note that digital inputs sclk , si and csn are high-impedance inputs (no internal pull-up) and should have external pull-ups if not driven. so is high-impedance w hen csn is high. external pull-up should be used at so to prevent floating input at microcontroller, or the internal so -pin pull-up should be enabled. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 14 of 85
smartrf ? CC2420 circuit description serial mi cr oco n t ro ll er in t e r f ac e ln a digi tal de m o dula t or - dig i t a l rs si - gain c ontr o l - ima g e s uppression - channel fi lter ing - d e m o dulation - f r a m e sy nchroniz a tion di g i t a l m o dula t or - data spr eading - modulation on-chi p bi as dig i t a l in te r f a c e with fifo bu ffer s , crc a n d en cr yp ti o n c o nt ro l log i c a u t o m a t i c g a in con t ro l t x p o w e r con t rol t x / r x c o nt ro l xo sc 16 mhz r ad c ad c da c da c 0 90 fr eq synth smar trf ? cc2 4 20 pow e r c ont rol pa se r i a l vo lt age regulator dig i t a l an d anal og test int e rf ace figure 2. CC2420 simplified block diagram a simplified block diagram of CC2420 is shown in figure 2. CC2420 features a low-if receiver. the received rf signal is amplified by the low- noise amplifier (lna) and down-converted in quadrature (i and q) to the intermediate frequency (if). at if (2 mhz), the complex i/q signal is filtered and amplified, and then digitized by the adcs. automatic gain control, final channel filtering, de- spreading, symbol correlation and byte synchronisation are performed digitally. when the sfd pin goes high, this indicates that a start of frame delimiter has been detected. CC2420 buffers the received data in a 128 byte receive fifo. the user may read the fifo through a spi interface. crc is verified in hardware. rssi and correlation values are appended to the frame. cca is available on a pin in receive mode. serial (unbuffered) data modes are also available for test purposes. the CC2420 transmitter is based on direct up-conversion. the data is buffered in a 128 byte transmit fifo (separate from the receive fifo). the preamble and start of frame delimiter are generated by hardware. each symbol (4 bits) is spread using the ieee 802.15.4 spreading sequence to 32 chips and output to the digital-to-analog converters (dacs). an analog lowpass filter passes the signal to the quadrature (i and q) upconversion mixers. the rf signal is amplified in the power amplifier (pa) and fed to the antenna. the internal t/r switch circuitry makes the antenna interface and matching very easy. the rf connection is differential. a balun may be used for single-ended antennas. the biasing of the pa and lna is done by connecting rxtx_switch to rf_p and rf_n through an external dc path. optionally one output can be turned off, giving a single ended output, but at the chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 15 of 85
smartrf ? CC2420 cost of reduced power level and receiver sensitivity. the frequency synthesizer includes a completely on-chip lc vco and a 90 degrees phase splitter for generating the i and q lo signals to the down-conversion mixers in receive mode and up-conversion mixers in transmit mode. the vco operates in the frequency range 4800 ? 4966 mhz, and the frequency is divided by two when split in i and q. a crystal must be connected to xosc16_q1 and xosc16_q2 and provides the reference frequency for the synthesizer. a digital lock signal is available from the pll. the digital baseband includes support for frame handling, address recognition, data buffering and mac security. the 4-wire spi serial interface is used for configuration and data buffering. an on-chip voltage regulator delivers the regulated 1.8 v supply voltage. the voltage regulator may be enabled / disabled through a separate pin. a battery monitor may optionally be used to monitor the unregulated power supply voltage. the battery monitor is configurable through the spi interface. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 16 of 85
smartrf ? CC2420 application circuit few external components are required for the operation of CC2420 . a typic a l application circuit is shown in figure 3. the external components are described in table 1 and typical values are given in table 2. input / output matching the rf input/output is high impedance and differential (optionally one output can be disabled for single-ended operation). the optimum differential load for the rf port is 115+j180 ? . when using an unbalanced antenna such as a monopole, a balun should be used in order to optimise performance. the balun can be implemented using low-cost discrete inductors and capacitors. the balun consists of c61, c62, c71, c81, l61, l62 and l72, and will match the rf input/output to 50 ? , see figure 3. l61 and l62 also provide dc biasing of the lna/pa input/output. an internal t/r switch circuit is used to switch between the lna and the pa. see input/output matching section on page 51 for more details. if a balanced antenna such as a folded dipole is used, the balun can be omitted. if the antenna also provides a dc path from txrx_switch pin to the rf pins, inductors are not needed for dc bias. figure 4 shows a typical application circuit with differential antenna. the dipole has a virtual ground point, hence bias is provided without degradation in antenna performance. a 27 nh series inductor may be connected to the txrx_switch pin to improve the transmitted evm, but is not necessary to comply with the requirements in [1]. bias resistor the bias resistor r451 is used to set an accurate bias current. cry s tal an external crystal with two loading capacitors (c381 and c391) is used for the crystal oscillator. see page 51 for details. voltage regulator the on chip voltage regulator supplies all 1.8 v power supply inputs. c42 is required for stability of the regulator. a series resistor may be used to comply with the esr requirement. pow e r supply decoupling and filtering proper power supply decoupling must be used for optimum performance. the placement and size of the decoupling capacitors and the power supply filtering are very important to achieve the best performance in an application. chipcon provides a compact reference design that should be followed very closely. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 17 of 85
smartrf ? CC2420 ref description c42 voltage regulator load capacitance c61 discrete balun and match, see page 51 c62 dc block to antenna and match c71 front-end bias decoupling and match, see page 51 c81 discrete balun and match, see page 51 c381 16mhz cry s tal load capacitor, see page 51 c391 16mhz cry s tal load capacitor, see page 51 l61 dc bias and match, see page 51 l62 dc bias and match, see page 51 l81 discrete balun and match, see page 51 r451 precision resistor for current reference generator xtal 16mhz cry s tal, see page 51 table 1. ov erv i ew of external components 35 34 33 32 31 30 29 28 27 26 25 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 qlp48 7x 7 CC2420 rf transceiver d sub_c ore d sub_p ads avdd_ adc dvdd_ adc dgu ard avdd_ if2 dgn d_gu ard avdd_ rf2 dg nd nc nc reset n rf_p rf_n avdd _pre avdd _rf1 txrx_ switc h avdd_ vco v co_gu ard avdd _sw gnd gnd nc nc vreg _out avdd _chp r_bia s avdd _if1 vre g_in v reg_e n xosc1 6_q1 xosc1 6_q2 at est2 at est1 nc a vdd_x osc16 csn fifo fifop cca sfd dvdd1 .8 sclk dvdd _ram si so dvd d3.3 nc xt al c391 c381 c61 c71 c62 ante nna ( 50 ohm ) l81 c81 l62 di gi ta l in tef a c e r451 3.3 v pow e r sup p ly l61 c4 2 figure 3. ty pical application circuit w i th discrete balun for single-ended operation chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 18 of 85
smartrf ? CC2420 35 34 33 32 31 30 29 28 27 26 25 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 qlp48 7x 7 CC2420 rf t r an sceiver d sub_core d sub_pads avdd_adc dvdd_adc dguard avdd_if2 dg nd_guard a vdd_rf2 dgn d nc nc r esetn rf_p rf_n avdd_pre avdd_rf1 txrx_switch avdd_vco vco_guard avdd_sw gnd gnd nc nc vre g_out avd d_chp r_ bias avd d_if1 vr eg_in vre g_en xosc 16_q1 xosc 16_q2 a test2 a test1 nc avdd_xo sc16 csn fifo fifop cca sfd dvdd1.8 sclk dvdd_ram si so dvdd3.3 nc xtal c391 c381 di gi t a l intef a ce r451 3.3 v pow e r supply l61 c42 fo l d e d dipole antenn a figure 4. ty pical application circuit w i th differential antenna (folded dipole) chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 19 of 85
smartrf ? CC2420 item single ended output, discrete balun differential antenna c42 10 f, 0.5 ? < esr < 5 ? 10 f, 0.5 ? < esr < 5 ? c61 0.5 pf, +/- 0.25pf, np0, 0402 not used c62 5.6 pf, +/- 0.25pf, np0, 0402 not used c71 5.6 pf, 10%, x5r, 0402 5.6 pf, 10%, x5r, 0402 c81 0.5 pf, +/- 0.25pf, np0, 0402 not used c381 22 pf, 5%, np0, 0402 22 pf, 5%, np0, 0402 c391 22 pf, 5%, np0, 0402 22 pf, 5%, np0, 0402 l61 7.5 nh, 5%, monolithic/multilay e r, 0402 27 nh, 5%, monolithic/multilay e r, 0402 l62 5.6 nh, 5%, monolithic/multilay e r, 0402 not used l81 7.5 nh, 5%, monolithic/multilay e r, 0402 not used r451 43 k ? , 1%, 0402 43 k ? , 1%, 0402 xtal 16 mhz cry s tal, 16 pf load (c l ), esr < 60 ? 16 mhz cry s tal, 16 pf load (c l ), esr < 60 ? table 2. bill of materials for the application circuits chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 20 of 85
smartrf ? CC2420 ieee 802.15.4 modulation format this section is meant as an introduction to the 2.4 ghz direct sequence spread spectrum (dsss) rf modulation format defined in ieee 802.15.4. for a complete des c r iption, pleas e refer to [1]. the modulation and spreading functions are illustrated at block level in figure 5 [1]. each byte is divided into two symbols, 4 bits each. the least significant symbol is trans mitted firs t. for multi-byte fields , the least significant byte is transmitted first, except for security related fields where the mos t s i gnific ant byte it trans mitted firs t. each symbol is mapped to one out of 16 pseudo-random sequences, 32 chips each. the chip to symbol mapping is shown in table 3. the chip sequence is then transmitted at 2 mchips/s, with the least significant chip (c 0 ) trans mitted firs t for each symbol. bi t - to- symbol symbol - to-c hip o-qpsk modu lator tra n smi t ted bit-strea m (lsb fi rst) modu lated sig nal figure 5. modulation and spreading functions [1] sy mbol chip sequence (c 0 , c 1 , c 2 , ? , c 31 ) 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 2 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 3 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 4 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 5 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 6 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 7 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 8 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 9 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 10 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 11 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 12 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 13 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 14 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 15 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 table 3. ieee 802.15.4 sy mbol-to-chip mapping [1] the modulation format is offset ? quadrature phase shift keying (o-qpsk) with half-sine chip shaping. this is equivalent to msk modulation. each chip is shaped as a half-sine, transmitted alternately in the i and q channels with one half chip period offset. this is illustrated for the zero-symbol in figure 6. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 21 of 85
smartrf ? CC2420 1 01 0 11 0 1 i- ph as e q-pha s e 1 00 1 10 0 1 0 00 11 0 0 1 0 11 00 1 0 1 t c 2t c figure 6. i / q phases w h en transmitting a zero-sy m bol chip sequence, t c = 0.5 s configuration overview CC2420 can be configured to achieve the best performance for different applications. through the programmable configuration registers the following key parameters can be programmed: ? receive / transmit mode ? rf channel selection ? rf output power ? power-down / power-up mode ? crystal oscillator power-up / power down ? clear channel assessment mode ? packet handling hardware support ? encryption / authentication modes evaluation softw are chipcon provides users of CC2420 with a software program, smartrf ? studio (windows interface) which may be used for performance and functionality evaluation. figure 7 shows the user interface of the CC2420 configuration software. tbd picture to be included figure 7. smartrf studio user interface chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 22 of 85
smartrf ? CC2420 4-w i re serial configuration and data interface CC2420 is configured via a simple 4-wire spi-compatible interface (pins si , so , sclk and csn ) where CC2420 is the slave. this interface is also used to read and write buffered data (see page 34). all address and data transfer on the spi interface is done most significant bit first. register access there are 33 16-bit configuration and status registers, 15 command strobe registers, and two 8-bit registers to access the separate transmit and receive fifos. each of the 50 registers is addressed by a 6-bit address. the ram/register bit (bit 7) must be cleared for register access. the read/write bit (bit 6) selects a read or a write operation and makes up the 8-bit address field together with the 6-bit address. in each register read or write cycle, 24 bits are sent on the si-line. the csn pin (chip select, active low) must be kept low during this transfer.the bit to be sent first is the ram/register bit (set to 0 for register access), followed by the r/w bit (0 for write, 1 for read). the following 6 bits are the address-bits (a5:0 ) . a5 is the mos t significant bit of the address and is sent first. the 16 data-bits are then transferred (d15:0), also msb first. see figure 8 for an illustration. the configuration registers can also be read by the microcontroller via the same configuration interface. the r/w bit must be set high to initiate the data read-back. CC2420 then returns the data from the addressed register on the 16 clock cycles following the register address. the so pin is used as the data output and must be configured as an input by the microcontroller. the timing for the programming is also shown in figure 8 with reference to table 4. the clocking of the data on si into the CC2420 is done on the positive edge of sclk . when the last bit, d0, of the 16 data-bits has been written, the data word is loaded in the internal configuration register. multiple registers may be written without releasing csn , as described in the multiple spi access section on page 27. the register data will be retained during a programmed power-down mode, but not when the power-supply is turned off (e.g. by disabling the voltage regulator using the vreg_en pin). the registers can be programmed in any order. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 23 of 85
smartrf ? CC2420 0 0 a5 a4 a3 a2 a0 a1 d w 15 d w 14 d w 13 d w 12 d w 11 d w 10 d w 9 d w 8 d w 7 d w 6 d w 5 d w 4 d w 3 d w 2 d w 1 d w 0 s7 s6 s5 s4 s3 s2 s0 s1 0 1 a5 a4 a3 a2 a0 a1 d r 15 d r 14 d r 13 d r 12 d r 11 d r 10 d r 9 d r 8 d r 7 d r 6 d r 5 d r 4 d r 3 d r 2 d r 1 d r 0 s7 s6 s5 s4 s3 s2 s0 s1 r e a d fr om r e gis t e r / rxfi fo : w r it e to reg i st er / r x f i f o : x x x x x d r 15 sclk csn si so si so t sp t ch t sd t hd t ns t cl 1 a6 a5 a4 a3 a2 a0 a1 b1 b0 0 x x x x x d w 7 d w 6 d w 5 d w 4 d w 3 d w 2 d w 1 d w 0 s7 s6 s5 s4 s3 s2 s0 s1 1 a6 a5 a4 a3 a2 a0 a1 d r 7 d r 6 d r 5 d r 4 d r 3 d r 2 d r 1 d r 0 s7 s6 s5 s4 s3 s2 s0 s1 r e a d one by te f r om ra m: (multi ple r e a d s al so poss i ble ) r e a d a nd w r i t e one by te t o ra m : (multipl e re a d / w r ites al so p o ss ible ) x x x x x d r 7 b1 b0 1 x x x x x x x si so si so d r 7 d r 6 d r 5 d r 4 d r 3 d r 2 d r 1 d r 0 d r 7 0 0 a5 a4 a3 a2 a0 a1 d w 7 d w 6 d w 5 d w 4 d w 3 d w 2 d w 1 d w 0 d w 7 d w 6 d w 5 d w 4 d w 3 d w 2 d w 1 d w 0 s7 s6 s5 s4 s3 s2 s0 s1 w r i t e to txfi fo: x x x si so s7 s6 s5 s4 s3 s2 s0 s1 s7 s6 s5 s4 s3 s2 s0 s1 s7 figure 8. spi timing diagram parameter sy mbol min max units conditions sclk , clock frequency f sclk 1 0 m h z sclk low pulse duration t cl 25 ns the minimum time sclk must be low . sclk high pulse duration t ch 25 ns the minimum time sclk must be high. csn setup time t sp 25 ns the minimum time csn must be low before the first positive edge of sclk . csn hold time t ns 25 ns the minimum time csn must be held low after the last negative edge of sclk . si setup time t sd 25 ns the minimum time data on si must be ready before the positive edge of sclk . si hold time t hd 25 ns the minimum time data must be held at si , after the positive edge of sclk . rise time t ri se 100 ns the maximum rise time for sclk and csn f a ll time t fa l l 100 ns the maximum fall time for sclk and csn note: the set-up- and hold-times refer to 50% of vdd. table 4. spi timing specification status by te during transfer of the register access byte, command strobes, the first ram address byte and data transfer to the txfifo, the CC2420 status byte is returned on the so pin. the status byte c ontains 6 status bits which are described in table 5. issuing a snop (no operation) command strobe may be used to read the status byte. it may also be read during access to chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 24 of 85
smartrf ? CC2420 chip functions such as register or fifo access. bit # name description 7 - reserved, ignore value 6 xosc16m_stable indicates w hether the 16 mhz oscillator is running or not 0 : the 16 mhz cry s tal oscillator is not running 1 : the 16 mhz cry s tal oscillator is running 5 tx_underflow indicates w hether an fifo underflow has occurred during transmission. must be cleared manually w i th a sflushtx command strobe. 0 : no underflow has occurred 1 : an underflow has occurred 4 enc_busy indicates w hether the encry ption module is busy 0 : encry p tion module is idle 1 : encry p tion module is busy 3 tx_active indicates w hether rf transmission is active 0 : rf transmission is idle 1 : rf transmission is active 2 lock indicates w hether the frequency sy nt hesizer pll is in lock or not 0 : the pll is out of lock 1 : the pll is in lock 1 rssi_valid indicates w hether the rssi value is valid or not. 0 : the rssi value is not valid 1 : the rssi value is valid, alw a y s true w hen reception has been enabled at least 8 sy m bol periods (128 us) 0 - reserved, ignore value table 5. status by te returned during address transfer and txfifo w r iting command strobes command strobes may be viewed as single byte instructions to CC2420 . by addressing a command strobe register internal sequences will be started. these commands must be used to enable the crystal oscillator, enable receive mode, start decryption etc. all 15 command strobes are listed in table 11 on page 61. when the crystal oscillator is disabled (idle state in figure 23 on page 40), only the sxoscon command strobe may be used. all other command strobes will be ignored and will have no effect. the crystal oscillator must stabilise (see the xosc16m_stable status bit in table 5) before other command strobes are accepted. the command strobe register is accessed in the same way as for a register write operation, but no data is transferred. that is, only the ram/register bit (set to 0), r/w bit (set to 0) and the 6 address bits (in the range 0x00 through 0x0e) are written. a command strobe may be followed by any other spi access without pulling csn high, and is executed on the last falling edge on sclk . ram access the internal 368 byte ram may be accessed through the spi interface. single or multiple bytes may be read or written sending the address part (2 bytes) only once. the address is then automatically incremented by the CC2420 hardware for each new byte. data is read and written one byte at a time, unlike register access where 2 bytes are always required after each address byte. the crystal oscillator must be running when accessing the ram. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 25 of 85
smartrf ? CC2420 the ram/register bit must be set high to enable ram access. the 9 bit ram address consists of tw o parts, b1:0 (msb) selecting one of the three memory banks and a7:0 (lsb) selecting the address within the selected bank. the ram is divided into three memory banks: txfifo (bank 0), rxfifo (bank 1) and security (bank 2). the fifo banks are 128 bytes each, while the security bank is 112 bytes. a6:0 is transmitted directly after the ram/register bit as shown in figure 8. for ram access, a second byte is also required before the data transfer. this byte contains b1:0 in bits 7 and 6, followed by the r/w bit (0 for read+write, 1 for read). bits 4 through 0 are don?t care as shown in figure 8. for ram write, data to be written must be input on the si pin directly after the second address byte. ram data read is output on the so pin simultaneously, but may be ignored by the user if only writing is of interes t. for ram read, the selected byte(s) are output on the so pin directly after the second address byte. see figure 9 for an illustration on how multiple ram bytes may be read or written in one operation. the ram memory space is shown in table 6. as with register data, data stored in ram will be retained during a programmed power-down mode, but not when the power-supply is turned off (e.g. by disabling the voltage regulator using the vreg_en pin). add r cs n : c o mm an d st robe : rea d o r w r i t e a w h o l e re gist er (1 6 bit ) : da ta 8msb ad dr da ta 8lsb re ad 8 msb of a reg i ste r : da ta 8msb ad dr mu ltiple regis t er read or w r ite da ta 8msb ad dr da ta 8lsb da t a 8msb da t a 8ls b .. . r ead or w r ite n by t es from/to rf fif o : dat a by t e 0 ad dr fi fo dat a by t e 1 da ta by te2 da t a by te3 dat a by te n- 2 da ta by te n- 1 ... add r mu ltip le co mm and stro bes : add r ad dr ... a ddr ad dr da ta 8msb a ddr dat a by t e n- 3 add r ... read or w r ite n by te s fro m /to ra m: ad drh ra m ad dr l ra m dat a a ddr da t a a ddr+1 dat a a ddr+2 da t a a ddr+n ... fifo an d ram a ccess m u st be ter m ia ted w i t h se tting the csn pin high. comm an d st rob e s an d re giste r ac cess may be f o llow e d by any oth e r acces s , since the y a r e com p lete d on the last n ega tive edge on scl k . t hey m a y h o w e v e r a l so be ter m in ate d w i th sett ing csn high, if de sira ble, e . g. for re adin g only 8 b i ts f r om a co nfig ura t ion reg i ster . note : figure 9. configuration registers w r ite and read operations v i a spi chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 26 of 85
smartrf ? CC2420 a ddress by te ordering name description 0x16f ? 0x16c - - n o t u s e d 0x16b ? 0x16a msb lsb shortadr 16-bit short address, used for address recognition. 0x169 ? 0x168 msb lsb panid 16-bit pan identifier, used for address recognition. 0x167 ? 0x160 msb lsb ieeeadr 64-bit ieee address of current node, used for address recognition. 0x15f ? 0x150 msb lsb cbcstate temporary storage for cbc-mac calculations 0x14f ? 0x140 msb (fl ags ) lsb txnonce / txctr transmitter nonce for in-line authentication and transmitter counter for in-line encry ption. 0x13f ? 0x130 msb lsb key1 encry p tion key 1 0x12f ? 0x120 msb lsb sabuf stand-alone encry ption buffer, for plaintext input and ciphertext output 0x11f ? 0x110 msb (fl ags ) lsb rxnonce / rxctr receiver nonce for in-line authentication or receiver counter for in-line decry ption. 0x10f ? 0x100 msb lsb key0 encry p tion key 0 0x0ff ? 0x080 msb lsb rxfifo 128 by tes receive fifo 0x07f ? 0x000 msb lsb txfifo 128 by tes transmit fifo table 6. CC2420 ram memory space fifo access the txfifo and rxfifo may be accessed through the txfifo (0x3e) and rxfifo (0x3f) registers. the txfifo is write only, but may be read back using ram access as described in the previous section. data is read and written one byte at a time, as with ram access. the rxfifo is both writeable and readable. writing to the rxfifo should however only be done for debugging or for using the rxfifo for security operations (decryption / authentication). the crystal oscillator must be running when accessing the fifos. when writing to the txfifo, the status byte (see table 5) is output for each new data byte on so , as shown in figure 8. this could be used to detect txfifo underflow (see section rf data buffering section on page 34) while writing data to the txfifo. multiple fifo bytes may be accessed in one operation, as with the ram access. fifo access can only be terminated by setting the csn pin high once it has been started. the fifo and fifop pins also provide additional information on the data in the receive fifo, as will be described in the microcontroller interface and pin description section on page 28. note that the fifo and fifop pins only apply to the rxfifo. the txfifo has its underflow flag in the status byte. the txfifo may be flushed by issuing a stxflush command strobe. similarly, a srxflush command strobe will flush the receive fifo. multiple spi access register access, command strobes, fifo access and ram access may be issued continuously without setting csn high. e.g. the user may issue a command strobe, a register wr ite and writing 3 bytes to the txfifo in one operation, as chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 27 of 85
smartrf ? CC2420 illustrated in figure 10. the only exception is that fifo and ram access must be terminated by setting csn high. cs n si ad dr ad dr da t a 8m s b da t a 8ls b da ta ad dr + 1 so ad dr txfifo da t a ad dr da t a ad dr +2 s t atus st at u s - - status status s t atus sta t us co m m a n d s t robe regi ster read txf i fo wr i t e figure 10. multiple spi access example microcontroller interface and pin description when used in a typical system, CC2420 will interface to a microcontroller. this microcontroller must be able to: ? program CC2420 into different modes, read and write buffered data, and read back status information via the 4-wire spi-bus configuration interface ( si , so , sclk and csn ). ? interface to the receive and transmit fifos using the fifo and fifop status pins. ? interfac e to the cca pin for clear channel assessment. ? interfac e to the sfd pin for timing information (particularly for beaconing networks). configuration interface a CC2420 to microcontroller interface example is shown in figure 11. the microcontroller uses 4 i/o pins for the spi configuration interface ( si , so , sclk and csn ). so should be connected to an input at the microcontroller. si , sclk and csn must be microcontroller outputs. preferably the microcontroller should have a hardware spi interface. the microcontroller pins connected to si , so and sclk can be shared with other spi-interface devices. so is a high impedance output as long as csn is not activated (active low). an internal pull-up on the so pin may be enabled in the iocfg0.so_pullup configuration bit. csn should have an external pull-up resistor or be set to a high level during power down mode in order to prevent the input from floating. si and sclk should be set to a defined level to prevent the inputs from floating. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 28 of 85
smartrf ? CC2420 cc2 42 0 c csn si so sc l k mo si mi s o sc lk gio2 fi fo fif o p cc a sf d gio 0 in terrupt gio 1 timer c a p t ur e figure 11. microcontroller interface example receiv e mode in receive mode, the sfd pin goes high after the start of frame delimiter (sfd) field has been completely received. if address recognition is disabled or is successf ul, t he sfd pin goes low again only after the last byte of the mpdu has been received. if the received frame fails address recognition, the sfd pin goes low immediately. this is illustrated in figure 12. the fifo pin is high when there is one or more data bytes in the rxfifo. the first byte to be stored in the rxfifo is the length field of the rece ived frame, i.e. the fifo pin is set high when the length field is written to the rxfifo. the fifo pin then remains high until the rxfifo is empty. if a previously received frame is completely or partially inside the rxfifo, the fifo pin will remain high until the rxfifo is empty. when address recognition is enabled, data should not be read out of the rxfifo before the address is completely received, since the frame may be automatically flushed if it fails address recognition. this may be handled by using the fifop pin rxfifo ov erflow the rxfifo can only contain a maximum of 128 bytes at a given time. this may be divided between multiple frames, as long as the total number of bytes is 128 or less. if an overflow occurs in the rxfifo, this is signaled to the microcontroller by setting the fifo pin low while the fifop pin is high. data already in the rxfifo will not be affected by the overflow, i.e. frames already received may be read out. a sflushrx command strobe is required after a rxfifo overflow to enable reception of new data. note that at least one byte should be read from the rxfifo prior to issuing the sflushrx command strobe. otherwise the fifo will be flushed, but the fifop pin will not go low before a byte is read. for security enabled frames, the mac layer must read the source address of the received frame before it can decide which key to use to decrypt or authenticate. this data must therefore not be overwritten even if it has been read out of the rxfifo by the microcontroller. if the secctrl0.rxfifo_protection control bit is s e t, CC2420 also protects the frame header of security enabled frames until decryption has been performed. if no mac security is used or if it is implemented outside the CC2420 , this bit may be cleared to achieve optimal use of the rxfifo. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 29 of 85
smartrf ? CC2420 pre a m b le sf d len gth da ta rece ived over r f sf d pin fi fo p i n f i fo p pin, if thr e sh old h i ghe r t han fra m e leng th f i fo p pin, if thr e sh old low e r t han fra m e leng th s f d d e t e c t e d l e n g t h b y t e r e c e i v e d l a s t m p d u b y t e r e c e i v e d pre a m b le sf d len gth da ta rece ived over r f sf d pin fi fo p i n fi fo p pin a d d r e s s r e g o c n i t i o n c o m p l e t e d mac pr oto c ol d a ta un it ( m pd u ) w i th cor r e c t ad dr ess ma c p r ot o c ol d a t a un i t ( m p d u) wi t h wr on g a d d r e s s figure 12. pin activ ity examples during receiv e transmit mode during transmit, the fifo and fifop pins are still only related to the rxfifo. the sfd pin is however active during transmission of a data frame, as shown in figure 13. the sfd pin goes high when the sfd field has been completely transmitted. it goes low again when the complete mpdu (as defined by the length field) has been transmitted or if an underflow is detected. see the rf data buffering section on page 34 for more information on txfifo underflow. as can be seen from comparing figure 12 and figure 13, the sfd pin behaves very similarly during reception and transmission of a data frame. if the sfd pins of the transmitter and the receiver are compared during the transmission of a data frame, a small delay of approximately 2 s can be seen because of bandwidth limitations in both the transmitter and the receiver. pr ea m b le sf d l eng th da ta tr an s m i t ted ov e r r f sf d pin s f d t r a n s m i t t e d l a s t m p d u b y t e t r a n s m i t t e d o r t x u n d e r f l o w ma c p r o t o c o l da t a un i t (mp du) s t x o n c o m m a n d s t r o b e 12 s y mb ol pe r i od s a u to m a ti c a l l y ge ne r a te d p r ea mb le an d s f d d a ta fet c h e d fro m tx f i fo crc g e n e r a te d by c c 2420 figure 13. pin activ ity example during transmit general control and status pins in receive mode, the fifop pin can be used to interrupt the microcontroller when a threshold has been exceeded or a complete frame has been received. this pin should then be connected to a microcontroller interrupt pin. in receive mode, the fifo pin can be used to detect if there is data at all in the receiv e fifo . chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 30 of 85
smartrf ? CC2420 the sfd pin can be used to extract the timing information of transmitted and received data frames. the sfd pin will go high when a start of frame delimiter has been completely detected / transmitted. the sfd pin should preferably be connected to a timer capture pin on the microcontroller. for debug purposes, the sfd and cca pins can be used to monitor several status signals as selected by the iocfg1 register. see table 12 for available signals. the polarity of fifo , fifop , sfd and cca can be controlled by the iocfg0 register (address 0x1c). demodulator, sy mbol sy nchroniser and data decision the block diagram for the CC2420 demodulator is shown in figure 14. channel filtering and frequency offset compensation is performed digitally. the signal level in the channel is estimated to generate the rssi level (see the rssi / energy detection section on page 45 for more information). data filtering is also included for enhanced performance. with the 40 ppm frequency accuracy requirement from [1], a compliant receiver must be able to compensate for up to 80 ppm or 200 khz. the CC2420 demodulator tolerates up to 300 khz offset without significant degradation of the receiver performance. soft decision is used at the chip level, i.e. the demodulator does not make a decision for each chip, only for each received symbol. de-spreading is performed using over sampled symbol correlators. symbol synchronisation is achieved by a continuous start of frame delimiter (sfd) search. when a sfd is detected, data is written to the rxfifo and may be read out by the microcontroller at a lower bit rate than the 250 kbps generated by the receiver. the CC2420 demodulator also handles symbol rate errors in excess of 120 ppm without performance degradation. resynchronisation is performed continuously to adjust for error in the incoming symbol rate. the mdmctrl1.corr_thr control bits should be written to 20 to set the threshold for detecting ieee 802.15.4 start of frame delimiters. di gi t a l i f cha nne l fil t er in g adc digital da ta fi lt e r in g f r equ ency o ffset c o mp ensa t i o n sy mbol co rr elat or s and sy nchr on i s a t i o n rssi ge ne ra t o r i / q ana l o g i f s i gn al dat a sy m b ol ou t p ut rss i aver ag e co rr elat i o n value ( m ay be u s ed f o r lq i) figure 14. demodulator simplified block diagram frame format CC2420 has hardware support for parts of the ieee 802.15.4 frame format. this s e c t ion gives a brief s u mmary to the ieee 802.15.4 frame format, and describes how CC2420 is s e t up to c o mply with this . chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 31 of 85
smartrf ? CC2420 figure 15 [1] shows a schematic view of the ieee 802.15.4 frame format. similar figures describing specific frame formats (data frames, beacon frames, acknowledgment frames and mac command frames) are included in [1]. ph y lay e r fr a m e c ontr o l fi e l d (f c f ) da t a s e qu en c e num b e r 2 1 by t e s : ad dr ess info rm ation 0 to 20 fram e p a yl oa d n f r am e c h e c k s e q uen ce (f c s ) 2 ma c he ad er (mh r ) mac p a yl oa d m ac foo t er (m fr) fr a m e len gth mac p r o t ocol dat a un it (m pdu ) star t of fr ame d e lim iter (s f d ) byte s: 1 1 5 + ( 0 to 20) + n pr ea m b l e s e q uen ce 4 s y nchr on i s ati o n h ead er (s hr) p h y h e a der ( p hr) ph y ser v ice d a ta u n it ( p s du) p h y pr oto c o l d a ta u n it ( p p du) 1 1 + (4 to 20 ) + n ma c lay e r figure 15. schematic v i ew of the ieee 802.15.4 frame format [1] sy nchronisation header the synchronisation header (shr) consists of the preamble sequence followed by the start of frame delimiter (sfd). in [1], the preamble sequence is defined to be 4 bytes of 0x00. the sfd is one byte, set to 0xa7. in CC2420 , the preamble length and sfd is configurable. the default values are compliant with [1]. changing these values will make the system non-802.15.4- compliant, which could be desirable in some cases. a synchronisation header is always transmitted first in all transmit modes. the preamble sequence length can be set by mdmctrl0.preamble_length , while the sfd is programmed in the syncword register. syncword is 2 bytes long, which gives the user some extra flexibility as described below. figure 16 shows how the CC2420 synchronisation header relates to the ieee 802.15.4 specification. the programmable preamble length only applies to transmission, it does not affect receive mode. the preamble length should not be set shorter than the default value. note that 2 of the 8 zero-symbols in the preamble sequence required by [1] are included in the syncword register so that the CC2420 preamble sequence is only 6 symbols long for compliance with [1]. two additional zero symbols in syncword make CC2420 c o mpliant with [1]. in reception, CC2420 synchronises to received zero-symbols and searches for the sfd sequence defined by the syncword register. the least significant sy mbols in syncword set to 0xf will be ignored, while symbols different from 0xf will be required for synchronisation. the default setting of 0xa70f thereby requires one additional zero-symbol for synchronisation. this will reduce the number of false frames detected due to noise. in receive mode CC2420 uses the preamble sequence for symbol synchronisation and frequency offset adjustments. the sfd is used for byte synchronisation, and is not part of the data stored in the receive buffer (rxfifo). chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 32 of 85
smartrf ? CC2420 0 7 a iee e 802 . 1 5.4 pre a mble sfd cc2 42 0 2( p reambl e_leng th + 1) zero sym bols 0 0 0 0 0 0 0 sw 0 sw 0 = s y n cwo rd[ 3: 0] sw 1 = s y n cwo rd[ 7: 4] sw 2 = s y n cwo rd[ 11 :8] sw 3 = s y n cwo rd[ 15 :12 ] sw1 sw 2 sw3 if di ff eren t f r om 'f ', el s e '0 ' if di ff eren t f r om 'f ', el s e '0 ' if di ff eren t f r om 'f ', el s e '0 ' if di ff eren t f r om 'f ', el s e '0 ' synch r onisa t i o n head er figure 16. transmitted sy nchronisation header length field the frame length field shown in figure 15 defines the number of bytes in the mpdu. note that the length field does not include the length field itself. it does however include the fcs (frame check sequence), even if this is inserted automatically by CC2420 hardware. it also includes the mic if authentication is used. the length field is 7 bits and has a maximum value of 127. the most significant bit in the length field is reserved [1], and should be set to zero. CC2420 hardware uses the length field both for transmission and reception, so this field must always be included even if implementing a proprietary (non 802.15-4) sy st em. in transmit mode, the length field is used for underflow detection, as described in the fifo access section on page 27. mac protocol data unit the fcf, data sequence number and address information follows the length field as shown in figure 15. together with the mac data payload and frame check sequence, they form the mac protocol data unit (mpdu). the format of the fcf is shown in figure 17. pleas e refer to [1] for details . there is no hardware support for the data sequence number, this field must be inserted and verified by software. CC2420 includes hardware address recognition, as described in the address recognition section on page 36. bits: 0-2 3 4 5 6 7-9 10-11 12-13 14-15 frame ty pe security enabled frame pending acknow ledge request intra pan r e s e r v e d d e s t i n a t i o n addressing mode r e s e r v e d s o u r c e addressing mode figure 17. format of the frame control field (fcf) [1] frame check sequence a 2-byte frame check sequence (fcs) follows the last mac payload byte as shown in figure 15. the fcs is calculated over the mpdu, i.e. t he length field is not part of the fcs. this field is automatically generated and verified by hardware when the modemctrl0.autocrc control bit is set. it is recommended to always have this enabled, except possibly for debug purposes. if cleared, crc generation and verification must be performed by software. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 33 of 85
smartrf ? CC2420 the fcs polynomial is [1]: x 16 + x 12 + x 5 + 1 the CC2420 hardware implementation is shown in figure 18. please refer to [1] for further details. in transmit mode the fcs is appended at the correct position defined by the length field. the fcs is not written to the txfifo, but stored in a separate 16-bit register. in receive mode the fcs is verified by hardware. the user is normally only interested in the correctness of the fcs, not the fcs sequence itself. the fcs sequence itself is therefore not written to the rxfifo during receive. instead, when modemctrl0.autocrc is set the two fcs bytes are replaced by the rssi value, average correlation value (used for lqi) and crc ok/not ok. this is illustrated in figure 19. the first fcs byte is replaced by the 8-bit rssi value. see the rssi section on page 45 for details. the 7 least significant bits in the last fcs byte are replaced by the average correlation value of the 8 first symbols of the received phy header (length field) and phy servic e data unit (psdu). this correlation value may be used as a basis for calculating the lqi. see the link quality indication section on page 46 for details. the most significant bit in the last byte of each frame is set high if the crc of the received frame is correct and low otherwise. r0 r1 r 2 r 3 r 4 r5 r6 r 7 r8 r9 r10 r 11 r1 2 r 1 3 r14 r 15 da t a input (l s b first) figure 18. CC2420 frame check sequence (fcs) hardw a re implementation [1] mpdu le ngth b y te n mp d u 1 mpdu 2 mpdu n- 2 rs si (si g n ed) crc / corr 7 6 5 4 3 2 1 0 bi t numbe r crc ok correl atio n va l ue (un s ig ned ) d a ta i n r x fi fo figure 19. data in rxfifo w h en mdmctrl0.autocrc is set rf data buffering CC2420 can be configured for different transmit and receive modes, as set in the mdmctrl1.tx_mode and mdmctrl1.rx_mode control bits. buffered mode (mode 0) will be used for normal operation of CC2420 , while other modes are available for test purposes. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 34 of 85
smartrf ? CC2420 buffered transm it m ode in buffered transmit mode (tx_mode 0), the 128 byte txfifo, located in CC2420 ram, is used to buffer data before transmission. a preamble sequence (defined in the frame format section below) is automatically inserted before the length field during transmission. the length field must always be the first byte written to the trans mit buffer for all frames . writing one or multiple bytes to the txfifo is described in the fifo access section on page 27. reading data from the txfifo is possible with ram access, but this does not remove the byte from the fifo. transmission is enabled by issuing a stxon or stxoncca command strobe. see the radio control state machine section on page 39 for an illustration of how the transmit command strobes affect the state of CC2420 . the stxoncca strobe is ignored if the channel is busy. see the clear channel assessment section on page 46 for details on cca . the preamble sequence is started 12 symbol periods after the command strobe. after the programmable start of frame delimiter has been transmitted, data is fetched from the txfifo. a txfifo underflow is issued if too few bytes are written to the txfifo. transmission is then automatically stopped. the underflow is indicated in the tx_underflow status bit, which is returned during each address byte and each byte written to the txfifo. the underflow bit is only cleared by issuing a sflushtx command strobe. the txfifo can only contain one data frame at a given time. after complete transmission of a data frame, the txfifo is automatically refilled with the last transmitted frame. issuing a new stxon or stxoncca command strobe will then cause CC2420 to retrans mit the last frame. writing to the txfifo after a frame has been transmitted will cause the txfifo to be automatically flushed before the new byte is written. the only exception is if a txfifo underflow has occurred, when a sflushtx command strobe is required. buffered receiv e mode in buffered receive mode (rx_mode 0), the 128 byte rxfifo, located in CC2420 ram, is used to buffer data received by the demodulator. accessing data in the rxfifo is described in the fifo access section on page 27. the fifo and fifop pins are used to assist the microcontroller in supervising the rxfifo. please note that the fifo and fifop pins are only related to the rxfifo, even if CC2420 is in transmit mode. multiple data frames may be in the rxfifo simultaneously, as long as the total number of bytes does not exceed 128. see the rxfifo overflow section on page 29 for details on how a rxfifo overflow is detected and signaled. un-buffered, serial mode un-buffered mode should be used for evaluation / debugging purposes only. buffered mode is recommended for all applications. in un-buffered mode, the fifo and fifop pins are reconfigured as data and data clock pins. the txfifo and rxfifo buffers are not used in this mode. a synchronous data clock is provided by CC2420 at the fifop pin, and the fifo pin is used as data input/output. the fifop clock frequency is 250 khz when active. this is illustrated in figure 20. in serial transmit mode ( mdmctrl1.tx_mode =1), a synchronisation sequence is inserted at the start of each frame by hardware, as in buffered mode. data is sampled by CC2420 on the positive edge of fifop and should be updated by the microcontroller on the negative edge of fifop . see figure 20 for an illustration of the timing in serial transmit mode. the sfd and cca pins retain their normal operation also in serial chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 35 of 85
smartrf ? CC2420 mode. CC2420 will remain in serial transmit mode until transmission is turned off manually. in serial receive mode ( mdmctrl1.rx_mode =1) by t e synchronisation is still performed by CC2420 . this means that the fifop clock pin will remain idle low until a start of frame delimiter has been detected. receive m o de: incom i ng / outgoing rf data sfd f ifop tr ansm i t m o de: pre a mble fifo (fr o m u c ) b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 s0 s1 f ifop f ifo (fr o m CC2420 ) b0 b1 b2 b3 b4 s2 b8 b9 b10 b11 4 u s figure 20. un-buffered test mode, pin activ ity address recognition CC2420 includes hardware support for address recognition, as specified in [1]. hardware address recognition may be enabled / disabled using the mdmctrl0.adr_decode control bit. address recognition is based on the following requirements, listed from section 7.5.6.2 in [1]: ? the frame type subfield shall not contain an illegal frame type ? if the frame type indicates that the frame is a beacon frame, the source pan identifier shall match mac panid unles s mac panid is equal to 0xffff, in which case the beacon frame shall be accepted regardless of the source pan identifier. ? if a destination pan identifier is included in the frame, it shall match macpanid or shall be the broadcast pan identifier (0xffff). ? if a short destination address is included in the frame, it shall match either macshortaddress or the broadcast address (0xffff). otherwise if an extended destination address is included in the frame, it shall match aextendedaddress. ? if only source addressing fields are included in a data or mac command frame, the frame shall only be accepted if the device is a pan coordinator and the source pan identifier matches mac panid. if any of the above requirements are not satisfied and address recognition is enabled, CC2420 will disregard the incoming frame and flush the data from the rxfifo. only data from the rejected frame is flushed, data from previously accepted frames may still be in the rxfifo. incoming frames with reserved frame types (fcf frame type subfield is 4, 5, 6 or 7) is however accepted if the reserved_frame_mode control bit in mdmctrl0 is s e t. in this c a s e , no further address recognition is performed on these chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 36 of 85
smartrf ? CC2420 frames. this option is included for future expansions of the ieee 802.15.4 standard. if a frame is rejected, CC2420 will only start searching for a new frame after the rejected frame has been completely received (as defined by the length field) to avoid detecting false sfds within the frame. the mdmctrl0.pan_coordinator control bit must be correctly set, since parts of the address recognition procedure requires knowledge about whether the current device is a pan coordinator or not. acknow ledge frames CC2420 includes hardware support for transmitting acknowledge frames, as specified in [1]. figure 21 shows the format of the acknowledge frame. if mdmctrl0.autoack is enabled, an acknowledge frame is transmitted for all incoming frames accepted by the address recognition with the acknowledge request flag set and a valid crc. autoack therefore does not make sense unless also adr_decode and autocrc are enabled. the sequence number is copied from the incoming frame. autoack may be used for non-beacon systems as long as the frame pending field (see figure 17) is cleared. the acknowledge frame is then transmitted 12 symbol periods after t he last symbol of the incoming frame. this is as specified by [1] for non-beacon networks. frame contr o l fiel d (fcf) data sequence num ber 2 1 fr am e check sequence (fcs) 2 m a c header (m hr) m a c footer (m fr) fr am e length start of fr am e deli m i ter (sfd) bytes: 1 1 pr eam bl e s equ ence 4 synchronisati on header (shr) p h y header ( p hr) figure 21. acknow ledge frame format [1] two command strobes, sack and sackpend are defined to transmit acknowledge frames with the frame pending field cleared or set, respectively. the acknowledge frame is only transmitted if the crc is v a lid. for systems using beacons, there is an additional timing requirement that the acknowledge frame transmission should be started on the first backoff-slot boundary (20 symbol periods) at least 12 symbol periods after t he last symbol of the incoming frame. this timing must be controlled by the micr ocontroller by issuing the sack and sackpend command strobe 12 symbol periods before the following backoff-slot boundary, as illustrated in figure 22. if a sack or sackpend command strobe is issued while receiving an incoming frame, the acknowledge frame is transmitted 12 symbol periods after the last symbol of the incoming frame. this should be used to transmit acknowledge frames in non-beacon networks. this timing is also illustrated in figure 22. using sackpend will set the pending data flag for automatically transmitted acknowledge frames using autoack . the pending flag will then be set also for future acknowledge frames, until a sack command strobe is issued. acknowledge frames may be manually transmitted using normal data transmission if desired. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 37 of 85
smartrf ? CC2420 ppdu ac kn owled g e n o n - be ac on ne tw ork t ack = 1 2 sy mb ol pe rio d s ppdu ac kn owled g e bea c o n ne tw ork t ack < 32 sy mb ol p e r i o d s 1 2 s y mb ol pe rio d s <= l a s t p p d u s y m b o l b a c k o f f s l o t b o u n d a r y 12 sy mb ol p e r i ods s a c k / s a c k p e n d figure 22. acknow ledge frame timing chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 38 of 85
smartrf ? CC2420 radio control state machine CC2420 has a built-in state machine that is used to switch between different operation states (modes). the change of state is done either by using command strobes or by internal events such as sfd detected in receive mode. the radio control state machine states are shown in figure 23. the numbers in brackets refer to the state number readable in the fsmstate status register. this functionality is primarily for test / debug purposes. before using the radio in either rx or tx mode, the voltage regulator and crystal oscillator must be turned on and become stable. the voltage regulator and crystal oscillator startup times are given in the electrical specifications section on page 8. the crystal oscillator is controlled by accessing the sxoscon / sxoscoff command strobes. the xosc16m_stable bit in the status register returned during address transfer indicates whether the oscillator is running and stable or not (see table 5). this status register can be polled when waiting for the oscillator to start. for test purposes, the frequency synthesizer (fs) can also be manually calibrated and started by using the stxcal command strobe register. this will not start a transmission before a stxon command strobe is issued. this is not shown in figure 23. enabling transmission is done by issuing a stxon or stxoncca command strobe. turning off rf can be accomplished by using one of the srfoff or sxoscoff command strobe registers. after res e t the CC2420 is in power down mode. all configurati on registers can then be programmed in order to make the chip ready to operate at the correct frequency and mode. due to the very fast start-up time, CC2420 can remain in power down until a transmission session is requested. as also described in the 4-wire serial configuration and data interface section on page 23, the crystal oscillator must be running in order to have access to the ram and fifos. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 39 of 85
smartrf ? CC2420 w a it for the speci f i ed cry s tal oscil l ator start-up ti me , or pol l the xosc16m_sta ble status bi t id le [0] s xos co n s t x o n xo sc _ o n [1] w a it unti l voltage regulator has powered u p vo lta ge regul ato r off v reg _e n set low vr eg _ e n set hi gh chip reset (pi n or r e gister ) al l state s sx os co ff command strobe al l state s except idl e sr fo ff tx_c ali b r a te [3 2] a l l rx states tx_p re amble [34 , 35 and 36] 8 or 12 sy mbol periods later preambl e an d s f d is t r ansmitt ed tx _fr a m e [37 , 38 and 39] tx fi fo d a ta i s transmi tted rx_calibr a t e [2 and 40] t r a n s m i s s i o n c o m p l e t e d s r x o n rx_s fd_ sea rch [3, 4, 5 and 6] rx_ f ra me [16 a nd 4 0 ] 12 sy mbol periods later sfd fou n d f r a m e r e c e i v e d o r f a il e d a d d r e s s r e c o g n i t i o n a u to matic or manua l acknow l edge request tx _ack_calibra te [48] 12 sy mbol periods later tx _ack_p rea m b l e [49, 5 0 and 51] tx_ a ck [52, 5 3 and 54] acknowled g e complet e d rx_ w a i t [14] cry s tal o scill ato r disa bled, regi ster access e nable d , f i f o / ra m access disabl ed s t x o n o r ( s t x o n c c a a n d c c a ) sa ck or sa ck pe n d figure 23. radio control states chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 40 of 85
smartrf ? CC2420 mac security operations (enc ry ption and authentication) CC2420 features hardware ieee 802.15.4 mac security operations. this includes counter mode (ctr) encryption / decryption, cbc-ma c authentication and ccm encryption + aut hentication. all security operations are based on aes encryption [2] using 128 bit keys. security operations are performed within the transmit and receive fifos on a frame basis. CC2420 also includes stand-alone aes encryption, in which one 128 bit plaintext is encrypted to a 128 bit ciphertext. the saes , stxenc and srxdec command strobes are used to start security operations in CC2420 as will be described in the following sections. the enc_busy status bit (see table 5) may be used to monitor when a security operation has been completed. security command strobes issued while the security engine is busy will be ignored, and the ongoing operation will be completed. table 6 on page 27 shows the CC2420 ram memory map, including the security related data located from addresses 0x100 through 0x15f. ram access (see the ram access section on page 25) is used to write or read the keys, nonces and stand-alone buffer. all security related data is stored little-endian, i.e. the least significant byte is transferred first over the spi interface during ram read or write operations. for a c o mplete des c r iption of ieee 802.15.4 mac security operations, please refer to [1]. key s all security operations are based on 128 bit keys. the CC2420 ram space has storage space for two individual keys (key0 and key1). transmit, receive and stand-alone encryption may select one of these two keys individually in the sec_txkeysel , sec_rxkeysel and sec_sakeysel control bits ( secctrl0 ). as can be seen from table 6 on page 27, key0 is located from address 0x100 and key1 from address 0x130. a way of establishing the keys used for encryption and authentication must be decided for each particular application. ieee 802.15.4 does not define how this is done, it is left to the higher layer of the protocol. zigbee uses an eliptic curve cryptography (ecc) based approach to establish keys. for pc based solutions, more processor intensive solutions such as diffie-hellman may be chosen. some applications may also use pre- programmed keys, e.g. for remote keyless entry where the key and lock are delivered in pairs. a push-button approach for loading keys may also be selected. nonce / counter the receive and transmit nonces used for encryption / decryption are located in ram from addresses 0x110 and 0x140 respectively. they are both 16 bytes. the nonce must be correctly initialized before receive or transmit ctr or ccm operations are started. the format of the nonce is shown in table 7. the block counter must be set to 1 for compliance with [1]. the key sequence counter is controlled by a layer above the mac layer. the frame counter must be increased for each new frame by the mac layer. the source address is the 64 bit ieee address. 1 by te 8 by tes 4 by tes 1 by te 2 by tes f l a g s s o u r c e address frame counter key sequence counter block counter table 7. ieee 802.15.4 nonce [1] the block counter bytes are not updated in ram, only in a local copy which is reloaded for each new in-line security operation. i.e. the block counter part of the nonce does not need to be rewritten. the CC2420 block counter should be set to 0x0001 for compliance with [1]. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 41 of 85
smartrf ? CC2420 CC2420 gives the user full flexibility in selecting the flags for both nonces. the flag setting is stored in the most significant byte of the nonce. the flag byte used for encryption and authentication is then generated as shown in figure 24. the frame counter part of the nonce must be incremented for each new packet by software. 7 6 ct r flag bits 7:6 5 4 3 2 1 0 - cbc flag bits 7:6 l 7 6 res 5 4 3 2 1 0 l 7 6 adata 5 4 3 2 1 0 m l 0 0 0 se cctrl 0.sec_ m m s b in CC2420 nonce ram ctr m ode flag byte cbc-m a c flag byte res res figure 24. CC2420 security flag by te stand-alone encry p tion plain aes encryption, with 128 bit plaintext and 128 bit keys [2], is available using stand-alone encryption. the plaintext is stored in stand-alone buffer located at ram location 0x120, as can be seen from table 6 on page 27. a stand-alone encryption operation is initiated by using the saes command strobe. the selected key ( secctrl0.sec_sakeysel ) is then used to encrypt the plaintext written to the stand-alone buffer. upon completion of the encryption operation, the ciphertext is written back to the stand-alone buffer, thereby overwriting the plaintext. note that ram write operations also output data currently in ram, so that a new plaintext may be written at the same time as reading out the previous ciphertext. in-line security operations CC2420 can do mac security operations (encryption, decrypt ion and authentication) on frames within the txfifo and rxfifo. these operations are called in- line security operations. as with other mac hardware support within CC2420 , in-line security operation relies on the length field in the phy header. a correct length field must therefore be used for all security operations. the key, nonce (does not apply to cbc- mac), and secctrl0 and secctrl1 cont rol regist ers must be correct ly set before starting any in-line security operation. the in-line security mode is set in secctrl0.sec_mode to one of the following modes: ? disabled ? cbc-mac (authentication) ? ctr (encryption / decryption) ? ccm (authentication and encryption / decryption) when enabled, tx in-line security is started in one of two ways: ? issue a stxenc command strobe. in- line security will be performed within the txfifo, but a rf transmission will not be started. ciphertext may be read back using ram read operations. ? issue a stxon or stxoncca command strobe. in-line security will be performed within the txfifo and a rf transmission of the ciphertext is started. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 42 of 85
smartrf ? CC2420 when enabled, rx in-line security is started as follows: ? issue a srxdec command strobe. the first frame in the rxfifo is then decrypted / authenticated as set by the current security mode. rx in-line security operations are always performed on the first frame currently inside the rxfifo, even if parts of this has already been read out over the spi interface. this allows the receiver to first read the source address out to decide which key to use before doing authentication of the complete frame. in ctr or ccm mode it is of course important that byte s to be decrypted are not read out before the security operation is started. when the srxdec command strobe is issued, the fifo and fifop pins will go low. this is to indicate to the microcontroller that no further data may be read out before the next byte to be read has undergone the requested security operation. the frame in the rxfifo may be received over rf or it may be written into the rxfifo over the spi interface for debugging or higher layer security operations. ctr mode encry p tion / decry p tion ctr mode encryption / decryption is performed by CC2420 on mac frames within the txfifo / rxfifo res pec tively. secctrl1.sec_txl / sec_rxl s e ts the number of bytes between the length field and the first byte to be encrypted / decrypted respectively. this controls the number of plaintext bytes in the current frame. for ieee 802.15.4 mac encryption, only the mac payload (see figure 15 on page 32) should be encrypted, so sec_txl / sec_rxl is set to 3 + (0 to 20) depending on the address information in the current frame. when encryption is init iated, the plaintext in the txfifo is then encrypted as specified by [1]. the encryption module will encrypt all the plaintext currently available, and wait if not everything is prebuffered. the encryption operation may also be started wit hout any data in the txfifo at all, and data will be encrypted as it is written to the txfifo. when decryption is initiated with a srxdec command strobe, the ciphertext of the rxfifo is then decrypted as specified by [1]. cbc-mac cbc-mac in-line authentication is provided by CC2420 hardware. secctrl0.sec_m sets the mic length m, encoded as (m-2)/2. when enabling cbc-mac in-line txfifo authentication, the generated mic is written to the txfifo for transmission. the frame length must include the mic. secctrl1.sec_txl / sec_rxl s e ts the number of bytes between the length field and the first byte to be authenticated, normally set to 0 for mac authentication. secctrl0.sec_cbc_head defines if the authentication length is used as the first byte of data to be authenticated or not. this bit should be set for compliance with [1]. when enabling cbc-mac in-line rxfifo authentication, the generated mic is compared to the mic in the rxfifo. the last byte of the mic is replaced in the rxfifo with: ? 0x00 if the mic is correct ? 0xff if the mic is incorrect the other bytes in the mic are left unchanged in the rxfifo. ccm ccm combines ctr mode encryption and cbc-mac authenticati on in one operation. ccm is described in [3]. secctrl1.sec_txl / sec_rxl s e ts the number of bytes after the length field to be authenticated but not encrytpted. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 43 of 85
smartrf ? CC2420 the mic is generated and verified very much like with cbc-mac described above. the only differences are from the requirements in [1] for ccm. timing table 8 shows some examples of the time used by the security module for different operations. mode l(a) l(m) l(mic) time [us] c c m 5 0 6 9 8 2 2 2 c t r - 1 5 - 9 9 c b c 1 7 9 8 1 2 9 9 stand- alone - 1 6 - 1 4 table 8. security timing examples chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 44 of 85
smartrf ? CC2420 linear if and agc settings CC2420 is based on a linear if chain where the signal amplification is done in an analog vga (variable gain amplifier). the gain of the vga is digitally controlled. the agc (automatic gain control) loop ensures that the adc operates inside its dynamic range by using an analog/digital feedback loop. the agc characteristics are set through the agcctrl , agctst0 , agctst1 and agctst2 registers. the reset values should be used for all agc control and t e st regist ers. rssi / energy detection CC2420 has a built-in rssi (received signal strength indicator) giving a digital value that can be read form the 8 bit, signed 2?s complement rssi.rssi_val register. the rssi value is always averaged over 8 symbol periods (128 s), in accordance with [1]. the rssi_valid status bit (table 5) indicates when the rssi value is valid, meaning that the receiver has been enabled for at least 8 symbol periods. the rssi register value rssi.rssi_val can be referred to the power p at the rf pins by using the following equations: p = rssi_val + rssi_offset [dbm] where the rssi_offset is found empirically during system development from the front end gain. rssi_offset is approximately ?45. e.g. if reading a value of ?20 from the rssi register, the rf input power is approximately ?65 dbm. a typical plot of the rssi_val reading as function of input power is shown in figure 25. it can be seen from the figure that the rssi reading from CC2420 is very linear and has a dynamic range of about 100 db. -60 -40 -20 0 20 40 60 -100 -80 - 60 -40 - 20 0 rf level [dbm ] rssi re gis t e r va lue figure 25. ty pical rssi v a lue v s . input pow er chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 45 of 85
smartrf ? CC2420 link quality indication the link quality indication (lqi) measurement is a characterisation of the strength and/or quality of a received packet, as defined by [1]. the rssi value described in the previous section may be used by the mac software to produce the lqi value. the lqi value is required by [1] to be limited to the range 0 through 255, with at least 8 unique values. software is responsible for generating the appropriate scaling of the lqi value for the given application. using the rssi value directly to calculate the lqi value has the disadvantage that e.g. a narrowband interferer inside the channel bandwidth will increase the lqi value although it actually reduces the true link quality. CC2420 therefore also provides an average correlation value for each incoming packet, based on the 8 first symbols following the sfd. this unsigned 7-bit value can be looked upon as a measurement of the ?chip error rate,? although CC2420 does not do chip decision. as described in the frame check sequence section on page 33, the average correlation value for the 8 first symbols is appended to each received frame together with the rssi and crc ok/not ok when mdmctrl0.autocrc is s e t. a c o rrelation value of ~110 indicates a maximum quality frame while a value of ~50 is typically the lowest quality frames detectable by CC2420 . software must convert the correlation value to the range 0-255 defined by [1], e.g. by calculating: lqi = (corr ? a ) b limited to the range 0-255, where a and b are found empirically based on per measurements as a function of the correlation value. a combination of rssi and correlation values may also be used to generate the lqi value. clear channel assessment the clear channel assessment signal is based on the measured rssi value and a programmable threshold. the clear channel assessment function is used to implement the csma-ca functionality specified in [1]. cca is valid when the receiver has been enabled for at least 8 symbol periods. carrier sense threshold level is programmed by rssi.cca_thr . the threshold value can be programmed in steps of 1 db. a cca hysteresis can also be programmed in the mdmctrl0.cca_hyst control bits. all 3 cca modes specified by [1] are implemented in CC2420 . they are set in mdmctrl0.cca_mode , as can be seen in the register description. the different modes are: 0 r e s e r v e d 1 clear channel w hen received energy is below threshold. 2 clear channel w hen not receiving valid ieee 802.15.4 data. 3 clear channel w hen energy is below threshold and not receiving valid ieee 802.15.4 data clear channel assessment is available on the cca output pin. cca is active high, but the polarity may be changed by setting the iocfg0.cca_polarity control bit. implementing csma-ca may easiest be done by using the stxoncca command strobe, as described in the radio control state machine section on page 39. transmission will then only start if the chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 46 of 85
smartrf ? CC2420 channel is clear. the tx_active status bit (see table 5) may be used to detect the result of the cca. frequency and channel programming the operating frequency is set by programming the 10 bit frequency word located in fsctrl.freq[9:0] . the operating frequency f c in mhz is given by: f c = 2048 + fsctrl.freq[9:0] mhz in receive mode the actual lo frequency is f c ? 2 mhz, since a 2 mhz if is used. direct conversion is used for transmission, so here the lo frequency equals f c . the 2 mhz if is automatically set by CC2420 , so the frequency programming is equal for rx and tx. ieee 802.15.4 specifies 16 channels within the 2.4 ghz band, numbered 11 through 26. the rf frequency of channel k is given by [1] : f c = 2405 + 5 (k-11) mhz, k=11, 12, ..., 26 for operation in channel k, the fsctrl.freq register should therefore be s e t to: fsctrl.freq = 357 + 5 (k-11) vco and pll self-calibration vco the vco is completely integrated and operates at 4800 ? 4966 mhz. the vco frequency is divided by 2 to generate frequencies in the desired band (2400- 2483.5 mhz). pll self-calibration the vco's characteristics will vary with temperature, changes in supply voltages, and the desired operating frequency. in order to ensure reliable operation the vco?s bias current and tuning range are automatically calibrated every time the rx mode or tx mode is enabled, i.e. in the rx_calibrate, tx_calibrate and tx_ack_calibrate c ontrol states in figure 23 on page 40. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 47 of 85
smartrf ? CC2420 output pow e r programming the rf output power of the device is programmable and is controlled by the txctrl.pa_level register. table 9 shows the output power for different settings, including the complete programming of the txctrl control register. the typical current consumption is also shown. the power amplifier can be operated in differential or single ended mode. in single ended mode only the rf_p output pin is used. the mode is controlled by txctrl.pa_diff . for highest possible output power use the differential mode by s e tting txctrl.pa_diff =1 (reset v a lue). pa_level txctrl register output pow e r [dbm] current consumption [ma ] 3 1 0 x a 0 f f 0 1 7 . 4 2 7 0 x a 0 f b - 1 1 6 . 5 2 3 0 x a 0 f 7 - 3 1 5 . 2 1 9 0 x a 0 f 3 - 5 1 3 . 9 1 5 0 x a 0 e f - 7 1 2 . 5 1 1 0 x a 0 e b - 1 0 1 1 . 2 7 0 x a 0 e 7 - 1 5 9 . 9 3 0 x a 0 e 3 - 2 5 8 . 5 table 9. output pow er settings and ty pical current consumption @ 2.45 ghz chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 48 of 85
smartrf ? CC2420 voltage regulator CC2420 includes a low drop-out voltage regulator. this is used to provide a 1.8 v power supply to the CC2420 power supplies. the voltage regulator should not be used to provide power to other circuits because of limited power sourcing capability and noise considerations. the voltage regulator input pin vreg_in is connected to the unregulated 2.1 to 3.6 v power supply. the voltage regulator is enabled / disabled using the active high voltage regulator enable pin vreg_en . the regulated 1.8 v voltage output is available on the vreg_out pin. a simplified schematic of the voltage regulator is shown in figure 26. the voltage regulator requires external components as described in the application circuit section on page 17. when disabling the voltage regulator, note that register and ram programming will be lost as leakage current reduces the output voltage on the vreg_out pin below 1.6 v. CC2420 should then be reset before the voltage regulator is disabled. vreg_i n inte rn al ba nd gap vo lt a g e re fer e n c e 1. 2 5 v vreg_ out vreg_ en re gu la to r en ab le / di sa bl e figure 26. voltage regulator, simplified schematic battery monitor the on-chip battery monitor enables monitoring the unregulated voltage on the vreg_in pin. it gives status information on the voltage being above or below a programmable threshold. a simplified schematic of the battery monitor is shown in figure 27. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 49 of 85
smartrf ? CC2420 vr eg _i n internal bandg ap vol t a g e reference 1.25 v b a t t m on. ba tt mo n_ vo lt ag e[4 :0 ] ba tt mo n. ba tt mo n_ ok ba tt mo n. ba tt mon _e n figure 27. battery monitor, simplified schematic the battery monitor is controlled through the battmon control register. the battery monitor is enabled and disabled using the battmon.battmon_en control bit. the voltage regulator must also be enabled when using the battery monitor. the battery monitor status bit is available in the battmon.battmon_ok status bit. this bit is high when the vreg_in input voltage is higher than the toggle voltage v toggle . the battery monitor toggle voltage is set in the 5-bit battmon.battmon_voltage control bits. battmon_voltage is an unsigned, positive number from 0 to 31. the toggle voltage is given by: 27 72 v 25 . 1 v toggle ltage battmon_vo ? ? = alternatively, for a desired toggle voltage, battmon_voltage should be set according to: v 25 . 1 27 72 v toggle ? ? = ltage battmon_vo the voltage regulator must be enabled for at least 100 s before the first measurement. after being enabled, the battmon_ok status bit need 2 s to settle for each new toggle voltage programmed. the main performance characteristics of the battery monitor is shown in the electrical specifications section on page 8. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 50 of 85
smartrf ? CC2420 cry s tal oscillator an external clock signal or the internal crystal oscillator can be used as main frequency reference. the reference frequency must be 16 mhz. because the crystal frequency is used as reference for the data rate as well as other internal signal processing functions, other frequencies cannot be used. if an external clock signal is used this should be connected to xosc16_q1 , while xosc16_q2 should be left open. the main.xosc16m_bypass bit must be set when an external clock signal is used. using the internal crystal oscillator, the crystal must be connected between the xosc16_q1 and xosc16_q2 pins. the oscillator is designed for parallel mode operation of the crystal. in addition, loading capacitors (c 381 and c 391 ) for the crystal are required. the loading capacitor values depend on the total load capacitance, c l , specified for the crystal. the total load capacitance seen between the crystal terminals should equal c l for the crystal to oscillate at the specified frequency. parasitic l c c c c + + = the parasitic capacitanc e is constituted by pin input capacitance and pcb stray capacitance. the total parasitic capacitance is typically 5 pf. a trimming capacitor may be placed across c 381 for initial tuning if necessary. the crystal oscillator circuit is shown in figure 28. typical component values for different values of c l are given in table 10. the crystal oscillator is amplitude regulated. this means that a high current is used to start up the oscillations. when the amplitude builds up, the current is reduced to what is necessary to maintain a stable oscillation. this ensures a fast start-up and keeps the drive level to a minimum. the esr of the crystal must be within the specification in order to ensure a reliable start-up (see the electrical specifications section). c3 8 1 c3 9 1 xt a l x o sc 16 _q 1 x o s c 16_ q2 c3 8 1 c3 9 1 xt a l xt a l x o sc 16 _q 1 x o s c 16_ q2 figure 28. cry s tal oscillator circuit item c l = 12 pf c l = 16 pf c l = 22 pf c6 6.8 pf 18 pf 27 pf c7 6.8 pf 18 pf 27 pf table 10. cry s tal oscillator component v a lues chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 51 of 85
smartrf ? CC2420 input / output matching the rf input / output is differential ( rf_n and rf_p ). in addition there is supply switch output pin ( txrx_switch ) that must have an external dc path to rf_n and rf_p . in rx mode the txrx_switch pin is at ground and will bias the lna. in tx mode the txrx_switch pin is at supply rail voltage and will properly bias the internal pa. the rf output and dc bias can be done using different topologies. some are shown in figure 3 and figure 4. component values are given in table 2. using a differential antenna, no balun is required. if a single ended output is required (for a single ended connector or a single ended antenna), a balun should be used for optimum performance. the balun can be realized using discrete inductors and capacitors, or a ltcc balun can be used. if the power amplifier is configured for single ended use, then a simpler matching network can be used. the output power and sensitivity will however be reduced. the rf_n pin should then be terminated in a grounded capacitor and the rf_p pin should have a dc path to the txrx_switch pin. transmitter test modes CC2420 can be set into different transmit test modes for performance evaluation. the test mode descriptions in the following sections requires that the chip is first reset, the crystal oscillator is enabled using the sxoscon command strobe and that the crystal oscillator has stabilised. unmodulated carrier an unmodulated carrier may be transmitted by setting mdmctrl1.tx_mode to 2, writing 0x1800 to the dactst register and issue a stxon command strobe. the transmitter is then enabled while the transmitter i/q dacs are overridden to static values. an unmodulated carrier will then be available on the rf output pins. a plot of the single carrier output spectrum from CC2420 is shown in figure 29 below. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 52 of 85
smartrf ? CC2420 a un it d b m rf a t t 30 d b 1avg 1s a re f lv l 3 db m re f lv l 3 db m ce nt er 2 . 4 5 gh z sp an 2 m h z 20 0 kh z/ rb w 1 0 kh z vb w 1 0 kh z sw t 5 0 ms -9 0 -8 0 -7 0 -6 0 -5 0 -4 0 -3 0 -2 0 -1 0 0 -9 7 3 da te : 2 3 . o c t . 2 0 0 3 21 :3 8: 33 figure 29. single carrier output modulated spectrum the CC2420 has a built-in test pattern generator that can generate pseudo random sequence using the crc generator. this is enabled by setting mdmctrl1.tx_mode to 3 and issue a stxon command strobe. the modulated spectrum is then available on the rf pins. the low by te of the crc word is transmitted and the crc is updated with 0xff for each new byte. the length of the transmitted data sequence is 65535 bits. the transmitted data-sequence is then: [synchronisation header] [0x00, 0x78, 0xb8, 0x4b, 0x99, 0xc3, 0xe9, ?] since a synchronisation header (preamble and sfd) is transmitted in all tx modes, this test mode may also be used to transmit a known pseudorandom bit sequence for bit error testing. please note that CC2420 requires symbol synchronisation, not only bit synchronisation, for correct reception. packet error rate is therefore a better measurement for the true rf performance. another option to generate a modulated spectrum is to fill the txfifo with pseudo- random data and set mdmctrl1.tx_mode to 3. CC2420 will then transmit data from the fifo disregarding a txfifo underflow. the length of the transmitted data sequence is then 1024 bits (128 bytes). a plot of the modulated spectrum from CC2420 is shown in figure 30. note that to find the output power from the modulated spectrum, the rbw must be set to 3 mhz or higher. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 53 of 85
smartrf ? CC2420 a un it d b m rf a t t 30 d b re f lv l 0 db m re f lv l 0 db m sw t 5 ms ce nt er 2 . 4 5 gh z sp an 1 0 mh z 1 mh z/ 1avg 1s a rb w 10 0 kh z vb w 10 0 kh z -9 0 -8 0 -7 0 -6 0 -5 0 -4 0 -3 0 -2 0 -1 0 -10 0 0 da te : 2 3 . o c t . 2 0 0 3 21 :3 4: 19 figure 30. modulated spectrum plot chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 54 of 85
smartrf ? CC2420 sy stem considerations and guidelines srd regulations international regulations and national laws regulate the use of radio receivers and transmitters. srds (short range devices) for license free operation are allowed to operate in the 2.4 ghz band worldwide. the most important regulations are en 300 440 (europe), fcc cfr-47 part 15.247 and 15.249 (usa), and arib std- t-66 (japan). frequency hopping and multi-channel sy stems the 2.4 ghz band is shared by many systems both in industrial, office and home environments. CC2420 uses direct sequence spread spectrum (dsss) as defined by [1] to spread the output power, thereby making the communication link more robust even in a noisy environment. with CC2420 it is also possible to combine both dsss and fhss (frequency hopping spread spectrum) in a proprietary non- ieee 802.15.4 system. this is achieved by reprogramming the operating frequency (see the frequency and channel programming section on page 47) before enabling rx or tx. a frequency synchronisation scheme must then be implemented within the proprietary mac layer to make the transmitter and receiver operate on the same rf channel. data burst transmissions the data buffering in CC2420 lets the user have a lower data rate link between the microcontroller and the rf device than the rf bit rate of 250 kbps. this allows the microcontroller to buffer data at its own speed, reducing the workload and timing requirements. the relatively high data rate of CC2420 also reduces the average power consumption compared to the 868 / 915 mhz bands defined by [1], where only 20 / 40 kbps are available. CC2420 may be powered up a smaller portion of the time, so that the average power consumption is reduced for a given amount of data to be transferred. cry s tal accuracy and drift a crystal accuracy of 40 ppm is required for compliance with ieee 802.15.4 [1]. this accuracy must also take ageing and temperature drift into consideration. a crystal with low temperature drift and low aging could be used without further compensation. a trimmer capacitor in the crystal oscillator circuit (in parallel with c7) could be used to set the initial frequency ac c u rately. for non-ieee 802.15.4 systems, the robust demodulator in CC2420 allows up to 120 ppm total frequency offset between the transmitter and receiver. this could e.g. relax the accuracy requirement to 60 ppm for each of the devices. optionally in a star network topology, the ffd could be equipped with a more accurate crystal thereby relaxing the requirement on the rfd. this can make sense in systems where the rfds ship in higher volumes than the ffds. communication robustness CC2420 provides very good adjacent, alternate and co channel rejection, image frequency suppression and blocking properties. the CC2420 performance is significantly better than the requirements imposed by [1]. these are highly important parameters for reliable operation in the 2.4 ghz band, since an increasing number of devices/systems are using this license free frequency band. communication security the hardware encryption and authentication operations in CC2420 enable secure communication, which is required for many applications. security operations require a lot of data processing which is costly in a 8-bit microcontroller system. the hardware support within chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 55 of 85
smartrf ? CC2420 CC2420 enables a high level of security even with a low-cost 8 bit controller. low cost sy stems as the CC2420 provides 250 kbps multi- channel performance without any external filters, a very low cost sy st em can be made. a differential antenna will eliminate the need for a balun, and the dc biasing can be achieved in the antenna topology. battery operated sy stems in low power applications, the CC2420 should be powered down when not being active. extremely low power consumption may be achieved when disabling also the voltage regulator. this will require reprogramming of the register and ram configuration. ber / per measurements CC2420 includes test modes where data is received infinitely and output to pins ( rx_mode 2, see page 35). this mode may be used for bit error rate (ber) measurements. however, the following actions must be taken to do such a measurement: ? a preamble and sfd sequence must be used, even if pseudo random data is transmitted, since receiving the dsss modulated signal requires sym bol synchronisation, not bit synchronisation like e.g. in 2fsk sy st ems. the syncword may be set to another value to fit to the measurement setup if necessary. ? the data transmitted over air must be spread according to [1] and the description on page 21. this means that the transmitter used during measurements must be able to do spreading of the bit data to chip data. remember that the chip sequence transmitted by the test setup is not the same as the bit sequence which is output by CC2420 . ? when operating at or below the sensitivity limit, CC2420 may lose symbol synchronisation in infinite receive mode. a new sfd and restart of the receiver may be required to re-gain synchronisation. in an ieee 802.15.4 system, all communication is based on packets. the sensitivity limit specified by [1] is based on packet error rate (per) measurements instead of ber. this is a more accurate measurement of the true rf performance since it mirrors the wa y the actual system operates. chipcon recommends performing per measurements instead of ber measurements to evaluate the performance of ieee 802.15.4 systems. to do per measurements, the following may be used as a guideline: ? a valid preamble, sfd and length field must be used for each packet . ? the psdu (see figure 15 on page 32) length should be 20 bytes for sensitivity measurements as specified by [1]. ? the sensitivity limit specified by [1] is the rf level resulting in a 1% per. the packet sample space for a given measurement must then be >> 100 to have a sufficiently large sample space. e.g. at least 1000 packets should be used to measure the sensitivity. ? the data transmitted over air must be spread according to [1] and the description on page 21. pre- generated packets may be used, although [1] requires that the per is averaged over random psdu data. ? the CC2420 receive fifo may be used to buffer data received during per measurements, since it is able to buffer up to 128 bytes. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 56 of 85
smartrf ? CC2420 ? the mdmctrl1.corr_thr control register should be set to 20, as described in the d e m o d u l a t o r , s y m b o l synchroniser and data decision sect ion. the simplest way of making a per measurement will be to use another CC2420 as the reference transmitter. however, this makes it difficult to measure the exact receiver performance. using a signal generator, this may either be s e t up as o-qpsk with half-s i ne shaping or as msk. if using o-qpsk, the phases must be selected according to [1]. if using msk, the chip sequence must be modified such that the modulated msk signal has the same phase shifts as the o- qpsk sequence previously defined. for a desired symbol sequence s 0 , s 1 , ? , s n-1 of length n symbols, the desired chip sequence c 0 , c 1 , c 2 , ?, c 32n-1 of length 32n is found using table lookup from table 3 on page 21. it can be seen from comparing the phase shifts of the o-qpsk signal with the frequency of a msk signal that the msk chip sequence is generated as: (c 0 xnor c 1 ), (c 1 xor c 2 ), (c 2 xnor c 3 ), ? , (c 32n-1 xor c 32n ) where c 32n may be arbitrarily selected. pcb lay out recommendations a four layer pcb is highly recommended. the second layer of the pcb should be the used as a ground plane. the top layer should be used for signal routing, and the open areas should be filled with metallisation connected to ground using several vias. the area under the chip is used for grounding and must be well connected to the ground plane with several vias. the ground pins should be connected to ground as close as possible to the package pin using individual vias. the de- coupling capacitors should also be placed as close as possible to the supply pins and connected to the ground plane by separate vias. supply power filtering is very important. the external components should be as small as possible (0402 is recommended) and surface mount devices must be used. caution should be used when placing the microcontroller in order to avoid interference with the rf circuitry. a development kit with a fully assembled evaluation module is available. it is strongly advised that this reference layout is followed very closely in order to get the best performance. the schematic, bom and layout gerber files for the reference designs are all available from the chipcon website. antenna considerations CC2420 can be used together with various types of antennas. a differential antenna like a dipole would be the easiest to interface not needing a balun (balanced to un-balanced transformation network). the length of the /2-dipole antenna is given by: l = 14250 / f where f is in mhz, giving the length in cm. an antenna for 2450 mhz should be 5.8 cm. each arm is therefore 2.9 cm. other commonly used antennas for short- range communication are monopole, helical and loop antennas. the single- ended monopole and helical would require a balun network between the differential output and the antenna. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 57 of 85
smartrf ? CC2420 monopole antennas are resonant antennas with a length corresponding to one quarter of the electrical wavelength ( /4). they are very easy to design and can be implemented simply as a ?piece of wire? or even integrated into the pcb. the length of the /4-monopole antenna is given by: l = 7125 / f where f is in mhz, giving the length in cm. an antenna for 2450 mhz should be 2.9 cm. non-resonant monopole antennas shorter than /4 can also be used, but at the expense of range. in size and cost critical applications such an antenna may very well be integrated into the pcb. enclosing the antenna in high dielectric constant material reduces the overall size of the antenna. many vendors offer such antennas intended for pcb mounting. helical antennas can be thought of as a combination of a monopole and a loop antenna. they are a good compromise in size critical applications. helical antennas tend to be more difficult to optimize than the simple monopole. loop antennas are easy to integrate into the pcb, but are less effective due to difficult impedance matching because of their very low radiation resistance. for low power applications the differential antenna is recommended giving the best range and because of its simplicity. the antenna should be connected as close as possible to the ic. if the antenna is located away from the rf pins the antenna should be matched to the feeding transmission line (50 ? ). chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 58 of 85
smartrf ? CC2420 configuration registers the configuration of CC2420 is done by programming the 16-bit configuration registers. complete descriptions of the registers are given in the following tables. after chip reset (from the resetn pin or programmable through the main.resetn configuration bit), all the registers have default values as shown in the tables. note that the main register is only reset by using the pin reset resetn . when writing to this register, all bits will get the value written, not the default value. this also means that the main.resetn bit must be written both low and then high to perform a chip reset through the serial interface. 15 registers are strobe command registers, listed first in table 11 below. accessing these registers will initiate the change of an internal state or mode. there are 33 normal 16-bits registers, also listed in table 11. many of these registers are for test purposes only, and need not be accessed for normal operation of CC2420 . the fifos are accessed through two 8-bit registers, txfifo and rxfifo . the txfifo register is write only. data may still be read out of the txfifo through regular ram access (see section ram access section on page 25), but data is then not removed from the fifo. note that the crystal oscillator must be active for all fifo and ram access. during the address transfer and while writing to the txfifo, a status byte is returned on the serial data output pin so . this status byte is described in table 5 on page 25. all configuration and st atus registers are described in the tables following table 11. a ddress register register ty pe description 0x00 snop s no operation (has no other effect than reading out status-bits) 0x01 sxoscon s turn on the cry s tal oscillator (set xo sc16m_pd = 0 and bias_pd = 0) 0x02 stxcal s enable and calibrate frequency sy nthesizer for tx; go from rx / tx to a w a it state w here only the sy nthesizer is running. 0x03 srxon s e n a b l e r x 0x04 stxon s enable tx after calibration (if not already performed) start tx in-line encry ption if spi_sec_mode 0 0x05 stxoncca s if cca indicates a clear channel: enable calibration, then tx. start in-line encry ption if spi_sec_mode 0 else do nothing 0x06 srfoff s disable rx/tx and frequency sy nthesizer 0x07 sxoscoff s turn off the cry s tal oscillator and rf 0x08 sflushrx s flush the rx fifo buffer and reset the demodulator. alw a y s read at least one by te from the rxfifo before issuing the sflushrx command strobe 0x09 sflushtx s flush the tx fifo buffer 0x0a sack s send acknow ledge frame, w i th pending field cleared. 0x0b sackpend s send acknow ledge frame, w i th pending field set. 0x0c srxdec s start rxfifo in-line decry ption / authentication (as set by spi_sec_mo d e) chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 59 of 85
smartrf ? CC2420 a ddress register register ty pe description 0x0d stxenc s start txfifo in-line encry ption / authentication (as set by spi_sec_mode), w i thout starting tx. 0x0e saes s aes stand alone encry ption strobe. spi_sec_mode is not required to be 0, but the encry ption module must be idle. if not, the strobe is ignored. 0x0f - - n o t u s e d 0x10 main r/w main control register 0x11 mdmctrl0 r/w modem control register 0 0x12 mdmctrl1 r/w modem control register 1 0x13 rssi r/w rssi and cca status and control register 0x14 syncword r/w sy nchronisation w o rd control register 0x15 txctrl r/w transmit control register 0x16 rxctrl0 r/w receive control register 0 0x17 rxctrl1 r/w receive control register 1 0x18 fsctrl r/w frequency sy nthesizer control and status register 0x19 secctrl0 r/w security control register 0 0x1a secctrl1 r/w security control register 1 0x1b battmon r/w battery monitor control and status register 0x1c iocfg0 r/w input / output control register 0 0x1d iocfg1 r/w input / output control register 1 0x1e manfidl r/w manufacturer id, low 16 bits 0x1f manfidh r/w manufacturer id, high 16 bits 0x20 fsmtc r/w finite state machine time constants 0x21 manand r/w manual signal and override register 0x22 manor r/w manual signal or override register 0x23 agcctrl r/w agc control register 0x24 agctst0 r/w agc test register 0 0x25 agctst1 r/w agc test register 1 0x26 agctst2 r/w agc test register 2 0x27 fstst0 r/w frequency sy nthesizer test register 0 0x28 fstst1 r/w frequency sy nthesizer test register 1 0x29 fstst2 r/w frequency sy nthesizer test register 2 0x2a fstst3 r/w frequency sy nthesizer test register 3 0x2b rxbpftst r/w receiver bandpass filter test register 0x2c fsmstate r finite state machine state status register 0x2d adctst r/w adc test register 0x2e dactst r/w dac test register 0x2f toptst r/w top level test register 0x30 reserved r/w reserved for future use control / status register 0x31- 0x3d - - not used chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 60 of 85
smartrf ? CC2420 a ddress register register ty pe description 0x3e txfifo w transmit fifo by te register 0x3f rxfifo r/w receiver fifo by te register r/w - read/w r ite (control/status), r - read only , w ? write only , s ? command strobe (perform action upon access) table 11. configuration registers ov erv i ew main (0x10) - main control register bit field name reset r/w description 1 5 r e s e t n 1 r / w active low reset of entire ci rcuit, should be applied before doing any thing else. equivalent to using the resetn reset pin. 1 4 e n c _ r e s e t n 1 r / w active low reset of the encry pt ion module. (test purposes only ) 1 3 d e m o d _ r e s e t n 1 r / w active low reset of the demodul ator module. (test purposes only ) 1 2 m o d _ r e s e t n 1 r / w active low reset of the modulat or module. (test purposes only ) 1 1 f s _ r e s e t n 1 r / w active low reset of the frequency sy nthesizer module. (test purposes only ) 1 0 : 1 - 0 w 0 reserved, w r ite as 0 0 x o s c 1 6 m _ b y p a s s 0 r / w by passes the cry s tal oscillator and uses a buffered version of the signal on q1 directly . this can be used to apply an external rail- rail clock signal to the q1 pin. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 61 of 85
smartrf ? CC2420 mdmctrl0 (0x11) - modem control register 0 bit field name reset r/w description 1 5 : 1 4 - 0 w 0 reserved, w r ite as 0 1 3 r e s e r v e d _ f r a m e _ m o d e 0 r/w mode for accepting reserved iee 802.15.4 frame ty pes w hen address recognition is enabled ( mdmctrl0.adr_decode = 1 ). 0 : reserved frame ty pes (100, 101, 110, 111) are rejected by address recognition. 1 : reserved frame ty pes (100, 101, 110, 111) are alw a y s accepted by address recognition. no further address decoding is done. when address recogniti on is disabled ( mdmctrl0.adr_decode = 0 ), all frames are received and reserved_frame_mode is don?t car e . 1 2 p a n _ c o o r d i n a t o r 0 r/w should be set high w hen the devic e is a pan coordinator. used for filtering packets w i th no desit ination address, as speccified in section 7.5.6.2 in 802.15.4, d18 1 1 a d r _ d e c o d e 1 r/w hardw a re address decode enable. 0 : address decoding is disabled 1 : address decoding is enabled 1 0 : 8 c c a _ h y s t [ 2 : 0 ] 2 r / w cca hy steresis in db, values 0 through 7 db 7 : 6 c c a _ m o d e [ 1 : 0 ] 3 r / w 0 : reserved 1 : cca=1 w hen rssi_val < cca_thr - cca_hyst cca=0 w hen rssi_val cca_thr 2 : cca=1 w hen not receiving valid ieee 802.15.4 data, cca=0 otherw i se 3 : cca=1 w hen rssi_val < cca_thr - cca_hyst andnot receiving valid ieee 802.15.4 data. cca=0 w hen rssi_val cca_thr or receiving a packet 5 a u t o c r c 1 r / w in packet mode a crc-16 (itu-t) is calculated and is transmitted after the last data by te in tx. in rx crc is calculated and checked for validity . 4 a u t o a c k 0 r / w if autoack is set, all packets accepted by address recognition w i th the acknow ledge request flag set and a valid crc are ack?ed 12 sy mbol periods after being received. 3 : 0 p r e a m b l e _ l e n g t h [3:0] 2 r / w the number of preamble by tes (2 zero-sy m bols) to be sent in tx mode prior to the sy ncword, encoded in steps of 2. the reset value of 2 is compliant w i th ieee 802.15.4, since the 4 th zer o by te is included in the sy ncword. 0 : 1 leading zero by tes (not recommended) 1 : 2 leading zero by tes (not recommended) 2 : 3 leading zero by tes (ieee 802.15.4 compliant) 3 : 4 leading zero by tes ? 15 : 16 leading zero by tes chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 62 of 85
smartrf ? CC2420 mdmctrl1 (0x12)? modem control register 1 bit field name reset r/w description 1 5 : 1 1 - 0 w 0 reserved, w r ite as 0. 10:6 c o r r _ t h r [ 4 : 0 ] 0 r/w demodulator correlator threshold value, required before sfd search. should alw a y s be set to 20. 5 d e m o d _ a v g _ m o d e 0 r / w frequency offset average filter behaviour. 0 : lock frequency offset filter after preamble match 1 : continuously update frequency offset filter. 4 m o d u l a t i o n _ m o d e 0 r / w set one of tw o rf modulation modes for rx / tx 0 : ieee 802.15.4 compliant mode 1 : reversed phase, non-ieee compliant (could be used to set up a sy stem w h ich w ill not receive 802.15.4 packets) 3 : 2 t x _ m o d e [ 1 : 0 ] 0 r / w set test modes for tx 0 : buffered mode, use txfifo (normal operation) 1 : serial mode, use transmit data on serial interface, infinite transmission. for lab testing only . 2 : txfifo looping ignore underflow in txfifo and read cy clic, infinite transmission. for lab testing only . 3 : send random data from crc, in finite transmission. for lab testing only . 1 : 0 r x _ m o d e [ 1 : 0 ] 0 r / w set test mode of rx 0 : buffered mode, use rxfifo (normal operation) 1 : receive serial mode, output received data on pins. infinite rx. for lab testing only . 2 : rxfifo looping ignore overflow in rxfifo and w r ite cy clic, infinite reception. for lab testing only . 3 : reserved rssi (0x13) - rssi and cca stat us and control register bit field name reset r/w description 1 5 : 8 c c a _ t h r [ 7 : 0 ] - 3 2 r / w clear channel assessment threshold value, signed number on 2?s complement for comparison w i th the rssi. the unit is 1 db, offset is the same as for rssi_val . the cca signal goes high w hen the received signal is below this value. the cca signal is available on the cca pin. the reset value is approximately -77 dbm. 7 : 0 r s s i _ v a l [ 7 : 0 ] - 1 2 8 r rssi estimate on a logarithmic scale, signed number on 2?s complement. unit is 1 db, offset is described in the rssi / energy detection section on page 45. the rssi_val value is averaged over 8 sy mbol periods. the rssi_valid status bit may be checked to verify that the receiver has been enabled for at least 8 sy mbol periods. the reset value of ?128 also indicates that the rssi_val value is invalid. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 63 of 85
smartrf ? CC2420 syncword (0x14) - sy nc word bit field name reset r/w description 1 5 : 0 s y n c w o r d [ 1 5 : 0 ] 0xa70f r/w sy nchronisation w o rd. the syncword is processed from the least significant nibble (f at reset) to the most significant nibble (a at reset). syncword is used both during modul ation (w here 0xf?s are replaced w i th 0x0?s) and duri ng demodulation (w here 0xf?s are not required for frame sy nchronisa tion). in reception an implicit zero is required before the first sy mbol required by syncword . the reset value is compliant w i th ieee 802.15.4. txctrl (0x15) - transmit control register bit field name reset r/w description 15:14 t x m i x b u f _ c u r [ 1 : 0 ] 1 r/w tx mixer buffer bias current. 0: 690ua 1: 980ua (nominal) 2: 1.16ma 3: 1.44ma 1 3 t x _ t u r n a r o u n d 1 r/w sets the w a it time after stxon before transmission is started. 0 : 8 sy mbol periods (128 us) 1 : 12 sy mbol periods (192 us) 12:11 t x m i x _ c a p _ a r r a y [ 1 : 0 ] 0 r/w selects varactor array settings in the transmit mixers. 1 0 : 9 t x m i x _ c u r r e n t [ 1 : 0 ] 0 r / w transmit mixers current: 0: 1.72 ma 1: 1.88 ma 2: 2.05 ma 3: 2.21 ma 8 : 6 p a _ c u r r e n t [ 2 : 0 ] 3 r / w current programming of the pa 0: -3 current adjustment 1: -2 current adjustment 2: -1 current adjustment 3: nominal setting 4: +1 current adjustment 5: +2 current adjustment 6: +3 current adjustment 7: +4 current adjustment 5 p a _ d i f f 1 r / w indicates w hether pa output is differential (1) or single-ended (0). 4 : 0 p a _ l e v e l [ 4 : 0 ] 3 1 r / w output pa level. (~0 dbm) chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 64 of 85
smartrf ? CC2420 rxctrl0 (0x16) ? receiv e control register 0 bit field name reset r/w description 1 5 : 1 4 - 0 w 0 reserved, w r ite as 0. 1 3 : 1 2 r x m i x b u f _ c u r [ 1 : 0 ] 1 r / w rx mixer buffer bias current. 0: 690ua 1: 980ua (nominal) 2: 1.16ma 3: 1.44ma 1 1 : 1 0 h i g h _ l n a _ g a i n [ 1 : 0 ] 0 r / w controls current in the lna gain compensation branch in agc high gain mode. 0: compensation disabled 1: 100 a compensation current 2: 300 a compensation current (nominal) 3: 1000 a compensation current 9 : 8 m e d _ l n a _ g a i n [ 1 : 0 ] 2 r / w controls current in the lna gain compensation branch in agc med gain mode. 7 : 6 l o w _ l n a _ g a i n [ 1 : 0 ] 3 r / w controls current in the lna gain compensation branch in agc low gain mode 5 : 4 h i g h _ l n a _ c u r r e n t [ 1 : 0 ] 2 r / w controls main current in the lna in agc high gain mode 0: 240 a lna current (x2) 1: 480 a lna current (x2) 2: 640 a lna current (x2) 3: 1280 a lna current (x2) 3 : 2 m e d _ l n a _ c u r r e n t [ 1 : 0 ] 1 r / w controls main current in the lna in agc med gain mode 1 : 0 l o w _ l n a _ c u r r e n t [ 1 : 0 ] 1 r / w controls main current in the lna in agc low gain mode chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 65 of 85
smartrf ? CC2420 rxctrl1 (0x17) - receiv e control register 1 bit field name reset r/w description 1 5 : 1 4 - 0 w 0 reserved, w r ite as 0. 1 3 r x b p f _ l o c u r 0 r / w controls reference bias current to rx bandpass filters: 0: 4 ua (default) 1: 3 ua 1 2 r x b p f _ m i d c u r 0 r / w controls reference bias current to rx bandpass filters: 0: 4 ua (default) 1: 3.5 ua 1 1 l o w _ l o w g a i n 1 r / w lna low gain mode setting in agc low gain mode. 1 0 m e d _ l o w g a i n 0 r / w lna low gain mode setting in agc medium gain mode. 9 h i g h _ h g m 1 r / w rx mixers high gain mode se tting in agc high gain mode. 8 m e d _ h g m 0 r / w rx mixers high gain mode setti ng in agc medium gain mode. 7 : 6 l n a _ c a p _ a r r a y [ 1 : 0 ] 1 r / w selects varactor array setting in the lna 0: off 1: 0.1pf (x2) (nominal) 2: 0.2pf (x2) 3: 0.3pf (x2) 5 : 4 r x m i x _ t a i l [ 1 : 0 ] 1 r / w control of the receiver mixers output current. 0: 12 a 1: 16 a (nominal) 2: 20 a 3: 24 a 3 : 2 r x m i x _ v c m [ 1 : 0 ] 1 r / w controls vcm level in the mixer feedback loop 0: 8 a mi xer c u rrent 1: 12 a mixer current (nominal) 2: 16 a mi xer c u rrent 3: 20 a mi xer c u rrent 1 : 0 r x m i x _ c u r r e n t [ 1 : 0 ] 2 r / w controls current in the mixer 0: 360 a mi xer c u rrent (x2) 1: 720 a mi xer c u rrent (x2) 2: 900 a mixer current (x2) (nominal) 3: 1260 a mi xer c u rrent (x2) chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 66 of 85
smartrf ? CC2420 fsctrl (0x18) - frequency sy nthesizer control and status bit field name reset r/w description 15:14 l o c k _ t h r [ 1 : 0 ] 1 r/w number of consecutive reference clock periods w i th successful sy nchronisation w i ndow s required to indicate lock: 0: 64 1: 128 (recommended) 2: 256 3: 512 1 3 c a l _ d o n e 0 r calibration has been performed since the last time the frequency sy nthesizer w a s turned on. 1 2 c a l _ r u n n i n g 0 r calibration status, '1' w hen calibration in progress and ?0? otherw i se. 1 1 l o c k _ l e n g t h 0 r / w sy nchronisation w i ndow pulse w i dth: 0: 2 prescaler clock periods (recommended) 1: 4 prescaler clock periods 1 0 l o c k _ s t a t u s 0 r frequency sy nthesizer lock status: 0 : frequency sy nthesizer is out of lock 1 : frequency sy nthesizer is in lock 9 : 0 f r e q [ 9 : 0 ] 3 5 7 (2405 mhz) r/w frequency control w o rd, contro lling the rf operating frequency f c . in transmit mode, the local oscillator (lo ) frequency equals f c . in receive mode, the lo frequency is 2 mhz below f c . f c = 2048 + freq[9:0] mhz see the frequency and channel programming section on page 47 for further information. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 67 of 85
smartrf ? CC2420 secctrl0 (0x19) - security control register bit field name reset r/w description 1 5 : 1 0 - 0 w 0 reserved, w r ite as 0 9 r x f i f o _ p r o t e c t i o n 1 r / w protection enable of the rxfifo, see description in the rxfifo overflow section on page 29. should be cleared if mac level security is not used or is implemented outside CC2420. 8 s e c _ c b c _ h e a d 1 r / w defines w hat to use for the first by te in cbc-mac (does not apply to cbc-mac part of ccm): 0 : use the first data by te as the first by te into cbc-mac 1 : use the length of the data to be authenticated (calculated as (the packet length field ? sec_txl ? 2) for tx or using sec_rxl for rx) as the first by te into cb c-mac (before the first data by te). this bit should be set high for cbc-mac 802.15.4 inline security . 7 s e c _ s a k e y s e l 1 r / w stand alone key select 0 : key 0 is used 1 : key 1 is used 6 s e c _ t x k e y s e l 1 r / w t x key select 0 : key 0 is used 1 : key 1 is used 5 s e c _ r x k e y s e l 0 r / w rx key select 0 : key 0 is used 1 : key 1 is used 4 : 2 s e c _ m [ 2 : 0 ] 1 r / w number of by tes in authentication field for cbc-mac, encoded as (m-2)/2 0 : reserved 1 : 4 2 : 6 3 : 8 4 : 10 5 : 12 6 : 14 7 : 16 1 : 0 s e c _ m o d e [ 1 : 0 ] 0 r / w security mode 0 : in-line security is disabled 1 : cbc-mac 2 : ctr 3 : ccm chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 68 of 85
smartrf ? CC2420 secctrl1 (0x1a) - security control register bit field name reset r/w description 1 5 - 0 w 0 reserved, w r ite as 0 14:8 sec_txl 0 r/w multi-purpose length by te for tx in-line security operations: ctr : number of cleartext by tes betw een length by te and the first by te to be encry pted cbc/mac : number of cleartext by tes betw een length by te and the first by te to be authenticated ccm : l(a), defining the number of by tes to be authenticated but not encry pted stand-alone : sec_txl has no effect 7 - 0 w 0 reserved, w r ite as 0 6 : 0 s e c _ r x l 0 r / w multi-purpose length by te for rx in-line security operations: ctr : number of cleartext by tes betw een length by te and the first by te to be decry pted cbc/mac : number of cleartext by tes betw een length by te and the first by te to be authenticated ccm : l(a), defining the number of by tes to be authenticated but not decry pted stand-alone : sec_rxl has no effect battmon (0x1b) ? battery monitor control register bit field name reset r/w description 1 5 : 7 - 0 w 0 reserved, w r ite as 0 6 b a t t _ o k 0 r battery monitor comparator output, read only . batt_ok is valid 5 us after battmon_en has been asserted and battmon_voltage has been programmed. 0 : pow e r supply < toggle voltage 1 : pow e r supply > toggle voltage 5 b a t t m o n _ e n 0 r / w battery monitor enable 0 : battery monitor is disabled 1 : battery monitor is enabled 4 : 0 b a t t m o n _ v o l t a g e [4:0] 0 r / w battery monitor toggle voltage. the toggle voltage is given by : 27 72 v 25 . 1 v toggle ltage battmon_vo ? ? = chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 69 of 85
smartrf ? CC2420 iocfg0 (0x1c) ? i/o configuration register 0 bit field name reset r/w description 1 5 : 1 2 - 0 w 0 reserved, w r ite as 0 1 1 - 0 r / w reserved, w r ite as 0 1 0 f i f o _ p o l a r i t y 0 r / w polarity of the output signal fifo. 0 : polarity is as described in the specification 1 : polarity is inverted as compared to the specification 9 f i f o p _ p o l a r i t y 0 r / w polarity of the output signal fifop. 0 : polarity is as described in the specification 1 : polarity is inverted as compared to the specification 8 s f d _ p o l a r i t y 0 r / w polarity of the sfd pin. 0 : polarity is as described in the specification 1 : polarity is inverted as compared to the specification 7 c c a _ p o l a r i t y 0 r/w polarity of the cca pin. 6:0 f i f o p _ t h r [ 6 : 0 ] 6 4 r/w fifop_thr sets the threshold in number of by tes in the rxfifo for fifop to go hi gh. iocfg1 (0x1d) ? i/o configuration register 1 bit field name reset r/w description 1 5 : 1 3 - 0 w 0 reserved, w r ite as 0 1 2 : 1 0 h s s d _ s r c [ 2 : 0 ] 0 r / w the hssd module is used as follow s : 0: off. 1: output agc status (gain setting / peak detector status / accumulator value) 2: output adc i and q values. 3: output i/q after digital dow nmix and channel filtering. 4: reserved 5: reserved 6: input adc i and q values 7: input dac i and q values. the hssd module requires that the fs is up and running as it uses clk_pre (~150 mhz) to produce its ~37.5 mhz data clock and serialize its output w o rds. 9 : 5 s f d m u x [ 4 : 0 ] 0 r / w multiplexer setting for the sfd pin. 4 : 0 c c a m u x [ 4 : 0 ] 0 r / w multiplexer setting for the cca pin. manfidl (0x1e) - manufacturer id, low er 16 bit bit field name reset r/w description 1 5 : 1 2 p a r t n u m [ 3 : 0 ] 2 r the device part number. CC2420 has part number 0x002. 1 1 : 0 m a n f i d [ 1 1 : 0 ] 0 x 3 3 d r gives the jedec manufacturer id . the actual manufacturer id can be found in manifid[7:1], the number of continuation by tes in manfid[11:8] and manfid[0]=1. chipcon's jedec manufacturer id is 0x7f 0x7f 0x7f 0x9e (0x1e preceeded by three continuation by tes.) chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 70 of 85
smartrf ? CC2420 manfidh (0x1f) - manufacturer id, upper 16 bit bit field name reset r/w description 1 5 : 1 2 v e r s i o n [ 3 : 0 ] 0 r version number. current number is 0. 1 1 : 0 p a r t n u m [ 1 5 : 4 ] 0 r the device part number. CC2420 has part number 0x002. fsmtc (0x20) - finite state machine time constants bit field name reset r/w description 1 5 : 1 3 t c _ r x c h a i n 2 r x [ 2 : 0 ] 3 r / w the time in 5 us steps betw een the time the rx chain is enabled and the demodulator and agc is enabled. the rx chain is started w hen the bandpass filter has been calibrated (after 6.5 sy mbol periods). 12:10 tc_switch2tx[2:0] 6 r/w the time in advance the pa is pow ered up before enabling tx. in s. 9 : 6 t c _ p a o n 2 t x [ 3 : 0 ] 1 0 r / w the time in advance the rxtx sw itch is set high, before enabling tx. in s. 5:3 tc_txend2switch[2:0] 2 r/w the time after the last chip in the packet is sent, and the rxtx sw itch is disabled. in s. 2:0 tc_txend2paoff[2:0] 4 r/w the time after the last chip in the packet is sent, and the pa is set in pow er-dow n. also the time at w h ich the modulator is disabled. in s. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 71 of 85
smartrf ? CC2420 manand (0x21) - manual signal and ov erride register 1 bit field name reset r/w description 1 5 v g a _ r e s e t _ n 1 r / w the vga_reset_n signal is used to reset the peak detectors in the vga in the rx chain. 1 4 b i a s _ p d 1 r/w reserved, w r ite as 0 1 3 b a l u n _ c t r l 1 r/w the balun_ctrl signal controls w hether the pa should receive its required ex ternal bias ing (1) or not (0) by controlling the rx/tx output sw itch. 1 2 r x t x 1 r/w rxtx signal: controls w hether t he lo buffers (0) or pa buffers (1) should be used. 1 1 p r e _ p d 1 r/w pow e rdow n of prescaler. 1 0 p a _ n _ p d 1 r/w pow e rdow n of pa (negative path). 9 p a _ p _ p d 1 r/w pow e rdow n of pa (positive path). when pa_n_pd=1 and pa_p_pd=1 the up-conversion mixers are in pow erdow n. 8 d a c _ l p f _ p d 1 r/w pow e rdow n of tx dacs. 7 x o s c 1 6 m _ p d 1 r / w 6 r x b p f _ c a l _ p d 1 r/w pow e rdow n control of complex bandpass receive filter calibration oscillator . 5 c h p _ p d 1 r/w pow e rdow n control of charge pump. 4 f s _ p d 1 r/w pow e rdow n control of vco, i/q generator, lo buffers. 3 a d c _ p d 1 r/w pow e rdow n control of the adcs. 2 v g a _ p d 1 r/w pow e rdow n control of the vga. 1 r x b p f _ p d 1 r / w pow e rdow n control of complex bandpass receive filter. 0 l n a m i x _ p d 1 r / w pow e rdow n control of lna, dow n-conversion mixers and frontend bias. 1 for some important signals the value used by analog and digital modules can be ove rridden manually . this is done as follow s for the hy pothetical important signal is : is_used = ( is * is_and_m ask) + is_o r_m ask , using boolean notation. the and-mask and or-mask for the important signals lis ted resides in the manand and manor registers, respectively . examples: ? writing 0xfffe to manand and 0x0000 to manor w ill force lnamix_pd 0 w hereas all other signals w ill be unaffected. ? writing 0xffff to manand and 0x0001 to manovr w ill force lnamix_pd 1 w hereas all other signals w ill be unaffected. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 72 of 85
smartrf ? CC2420 manor (0x22) - manual signal or ov erride register bit field name reset r/w description 1 5 v g a _ r e s e t _ n 0 r / w the vga_reset_n signal is used to reset the peak detectors in the vga in the rx chain. 1 4 b i a s _ p d 0 r / w global bias pow er dow n (1) 1 3 b a l u n _ c t r l 0 r/w the balun_ctrl signal controls w hether the pa should receive its required ex ternal biasing (1 ) or not (0) by controlling the rx/tx output sw itch. 1 2 r x t x 0 r/w rxtx signal: controls w hether t he lo buffers (0) or pa buffers (1) should be used. 1 1 p r e _ p d 0 r/w pow e rdow n of prescaler. 1 0 p a _ n _ p d 0 r/w pow e rdow n of pa (negative path). 9 p a _ p _ p d 0 r/w pow e rdow n of pa (positive path). when pa_n_pd =1 and pa_p_pd=1 the up-conversion mixers are in pow erdow n. 8 d a c _ l p f _ p d 0 r/w pow e rdow n of tx dacs. 7 x o s c 1 6 m _ p d 0 6 r x b p f _ c a l _ p d 0 r/w pow e rdow n control of complex bandpass receive filter calibration oscillator . 5 c h p _ p d 0 r/w pow e rdow n control of charge pump. 4 f s _ p d 0 r/w pow e rdow n control of vco, i/q generator, lo buffers. 3 a d c _ p d 0 r/w pow e rdow n control of the adcs. 2 v g a _ p d 0 r/w pow e rdow n control of the vga. 1 r x b p f _ p d 0 r / w pow e rdow n control of complex bandpass receive filter. 0 l n a m i x _ p d 0 r / w pow e rdow n control of lna, dow n-conversion mixers and frontend bias. agcctrl (0x23) - agc control bit field name reset r/w description 1 5 : 1 2 - 0 w 0 reserved, w r ite as 0 1 1 v g a _ g a i n _ o e 0 r / w use the vga_gain value during rx instead of the agc value. 1 0 : 4 v g a _ g a i n [ 6 : 0 ] 0 x 7 f r / w when w r itten, vga manual gain ov erride value; w hen read, the currently used vga gain setting. 3 : 2 l n a m i x _ g a i n m o d e _ o [1:0] 0 r / w lna / mixer gain mode override setting 0 : gain mode is set by agc algorithm 1 : gain mode is alw a y s low - gain 2 : gain mode is alw a y s med-gain 3 : gain mode is alw a y s high-gain 1 : 0 l n a m i x _ g a i n m o d e [1:0] 0 r status bit, defining the currently selected gainmode selected by the agc or overridden by the lnamix_gainmode_o setting. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 73 of 85
smartrf ? CC2420 agctst0 (0x24) - agc test register 0 bit field name reset r/w description 1 5 : 1 2 l n a m i x _ h y s t [ 3 : 0 ] 3 r / w hy steresis on the sw itching betw een different rf frontend gain modes, defined in 2 db steps 1 1 : 6 l n a m i x _ t h r _ h [ 5 : 0 ] 2 5 r / w threshold for sw itching betw een medium and high rf frontend gain mode, defined in 2 db steps 5 : 0 l n a m i x _ t h r _ l [ 5 : 0 ] 9 r / w threshold for sw itching betw een low and medium rf frontend gain mode, defined in 2 db steps agctst1 (0x25) - agc test register 1 bit field name reset r/w description 1 5 - 0 w 0 reserved, w r ite as 0 1 4 a g c _ b l a n k _ m o d e 0 r / w set the vga blanking mode w hen sw itching out a gainstage when vga_gain_oe = 0: 0 : blanking is performed w hen the agc algorithm sw itches out one or more 14db gain stages. 1 : blanking is never performed. when vga_gain_oe = 1: blanking is performed w hen agc_blank_mode =1 1 3 p e a k d e t _ c u r _ b o o s t 0 r / w doubles the bias current in t he peak-detectors in-betw een the vga stages w hen set. 1 2 : 1 1 a g c _ s e t t l e _ w a i t [ 1 : 0 ] 1 r / w timing for agc to w a it for analog gain to settle. 1 0 : 8 a g c _ p e a k _ d e t _ m o d e [2:0] 0 r / w sets the agc mode for use of the vga peak detectors: bit 2 : digital adc peak detector enable / disable bit 1 : analog fixed st ages peak detector enable / disable bit 0 : analog varliable gai n stage peak detector enable / disable 7 : 6 a g c _ w i n _ s i z e [ 1 : 0 ] 1 r / w window size for the accumulate and dump function in the ag c. 0 : 8 samples 1 : 16 samples 2 : 32 samples 3 : 64 samples 5 : 0 a g c _ r e f [ 5 : 0 ] 2 0 r / w target value for the agc contro l loop, given in 2 db steps. reset value corresponds to approximately 25% of the adc dy namic range in reception. agctst2 (0x26) - agc test register 2 bit field name reset r/w description 1 5 : 1 0 - 0 w 0 reserved, w r ite as 0 9 : 5 m e d 2 h i g h g a i n [ 4 : 0 ] 9 r / w med2highgain sets the difference in the receiver lna/mixer gain from medium gain mode to high gain mode, used by the agc for setting the correct frontend gain mode. 4 : 0 l o w 2 m e d g a i n [ 4 : 0 ] 1 0 r / w low2medgain sets the difference in the receiver lna/mixer gain from low gain mode to medium gain mode, used by the agc for setting the correct frontend gain mode. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 74 of 85
smartrf ? CC2420 fstst0 (0x27) - frequency sy nthesizer test register 0 bit field name reset r/w description 1 5 : 1 2 - 0 w 0 reserved, w r ite as 0 1 1 v c o _ a r r a y _ s e t t l e _ l o n g 0 r/w when '1' this control bit doubles the time allow ed for vco settling during vco calibration. 1 0 v c o _ a r r a y _ o e 0 r / w vco array manual override enable. 9 : 5 v c o _ a r r a y _ o [ 4 : 0 ] 1 6 r / w vco array override value. 4 : 0 v c o _ a r r a y _ r e s [ 4 : 0 ] - r the resulting vco array setting from the last calibration. fstst1 (0x28) - frequency sy nthesizer test register 1 bit field name reset r/w description 1 5 v c o _ t x _ n o c a l 0 r / w 0 : vco calibration is alw a y s performed w hen going to rx or w hen going to tx. 1 : vco calibration is only performed w hen going to rx or w hen using the stxcal command strobe 1 4 v c o _ a r r a y _ c a l _ l o n g 1 r/w when ?1? this control bit doubles the time allow ed for vco frequency measurements during vco calibration. 0 : pll calibration time is 37 us 1 : pll calibration time is 57 us 13:10 v c o _ c u r r e n t _ r e f [ 3 : 0 ] 4 r/w the value of the reference current calibrated against during vco calibr a tion. 9 : 4 v c o _ c u r r e n t _ k [ 5 : 0 ] 0 r / w vco current calibration constant. (current b override value w hen fstst2.vco_current_oe=1.) 3 v c _ d a c _ e n 0 r / w controls the source of the vco vc node in normal operation (pamtst.vc_in_test_en=0): 0: loop filter (closed loop pll) 1: vc dac (open loop pll) 2 : 0 v c _ d a c _ v a l [ 2 : 0 ] 2 r / w vc dac output value fstst2 (0x29) - frequency sy nthesizer test register 2 bit field name reset r/w description 1 5 - 0 w 0 reserved, w r ite as 0. 14:13 v c o _ c u r c a l _ s p e e d [ 1 : 0 ] 0 r/w vco current calibration speed: 0: normal 1: double speed 2: half speed 3: undefined. 1 2 v c o _ c u r r e n t _ o e 0 r / w vco current manual override enable. 11:6 v c o _ c u r r e n t _ o [ 5 : 0 ] 2 4 r/w vco current override value (current a). 5:0 v c o _ c u r r e n t _ r e s [ 5 : 0 ] - r the resulting vco current setting from last calibration. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 75 of 85
smartrf ? CC2420 fstst3 (0x2a) - frequency sy nthesizer test register 3 bit field name reset r/w description 1 5 c h p _ c a l _ d i s a b l e 1 r / w disable charge pump during vco calibration w hen set. 1 4 c h p _ c u r r e n t _ o e 0 r / w charge pump current override enable 0 : charge pump current set by calibration 1 : charge pump current set by start_chp_current 1 3 c h p _ t e s t _ u p 0 r / w forces the chp to output "up" current w hen set 1 2 c h p _ t e s t _ d n 0 r / w forces the chp to output "dow n" current w hen set 1 1 c h p _ d i s a b l e 0 r / w set to manually disable charge pump by masking the up and dow n pulses from the phase-detector. 1 0 p d _ d e l a y 0 r / w selects short or long reset delay in phase detector: 0: short reset delay 1: long reset delay 9:8 c h p _ s t e p _ p e r i o d [ 1 : 0 ] 2 r/w the charge pump current value step period: 0: 0.25 us 1: 0.5 us 2: 1 us 3: 4 us 7:4 s t o p _ c h p _ c u r r e n t [ 3 : 0 ] 1 3 r/w the charge pump current to stop at after the current is stepped dow n from start_chp_current after vco calibration is complete. the current is stepped dow n periodically w i th intervals as defined in chp_step_period. 3:0 s t a r t _ c h p _ c u r r e n t [ 3 : 0 ] 1 3 r/w the charge pump current to start w i th after vco calibration is complete. the current is then stepped dow n periodically to the value stop_chp_current w i th intervals as defined in chp_step_perio d. also used for overriding t he charge pump current w hen chp_current_oe=?1? rxbpftst (0x2b) - receiv e r bandpass filters test register bit field name reset r/w description 1 5 - 0 w 0 reserved, w r ite as 0. 1 4 r x b p f _ c a p _ o e 0 r / w rx bandpass filter capacitance calibration override enable. 1 3 : 7 r x b p f _ c a p _ o [ 6 : 0 ] 0 r / w rx bandpass filter capacitance calibration override value. 6 : 0 r x b p f _ c a p _ r e s [ 6 : 0 ] - r rx bandpass filter capacitance calibration result. 0 minimum capacitance in the feedback. 1: second smallest capacitance setting. ? 127: maximum capacitance in the feedback. fsmstate (0x2c) - finite state machine information bit field name reset r/w description 1 5 : 6 - 0 w 0 reserved, w r ite as 0. 5 : 0 f s m _ c u r _ s t a t e [ 5 : 0 ] - r gives the current state of the fifo and frame control (ffctrl) finite state machine. see the r adio control state machine section on page 39 for details. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 76 of 85
smartrf ? CC2420 adctst (0x2d) - adc test register bit field name reset r/w description 1 5 a d c _ c l o c k _ d i s a b l e 0 r / w adc clock disable 0 : clock enabled w hen adc enabled 1 : clock disabled, even if adc is enabled 1 4 : 8 a d c _ i [ 6 : 0 ] - r read the current adc i-branch value. 7 - 0 w 0 reserved, w r ite as 0. 6 : 0 a d c _ q [ 6 : 0 ] - r read the current adc q-branch value. dactst (0x2e) - dac test register bit field name reset r/w description 1 5 - 0 w 0 reserved, w r ite as 0. 1 4 : 1 2 d a c _ s r c [ 2 : 0 ] 0 r / w the tx dacs data source is selected by dac_src according to: 0: normal operation (from modulator). 1: the dac_i_o and dac_q_o override values below .- 2: from adc, most significant bits 3: i/q after digital dow nm ixing and channel filtering. 4: full-spectrum white noise (from crc) 5: from adc, leas t significant bits 6: rssi / cordic magnitude output 7: hssd module. this feature w ill often require the dacs to be manually turned on in manovr and pamtst.atestmod_mode=4. 1 1 : 6 d a c _ i _ o [ 5 : 0 ] 0 r / w i-branch dac override value. 5 : 0 d a c _ q _ o [ 5 : 0 ] 0 r / w q-branch dac override value. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 77 of 85
smartrf ? CC2420 toptst (0x2f) - top lev e l test register bit field name reset r/w description 1 5 : 8 - 0 w 0 reserved, w r ite as 0. 7 r a m _ b i s t _ r u n 0 r/w enable bist of the ram 0 : ram bist disabled, normal operation 1 : ram bist enabled. result output to pin, as set in iocfg1. 6 t e s t _ b a t t m o n _ e n 0 r/w enable test output of the battery monitor. 5 v c _ i n _ t e s t _ e n 0 r/w when atestmod_mode=7 this c ontrols w hether the atest2 in is used to output the vc node voltage (0) or to control the vc node voltage (1). 4 a t e s t m o d _ p d 1 r/w pow e rdow n of analog test module. 0 : pow e r up 1 : pow e r dow n 3:0 a t e s t m o d _ m o d e [ 3 : 0 ] when atestmod_pd =0, the function of the analog test module is as follow s : 0: outputs ?i? ( atest1 ) and ?q? ( atest2 ) from rxmix. 1: inputs ?i? ( atest2 ) and ?q? ( atest1 ) to bpf. 2: outputs ?i? ( atest1 ) and ?q? ( atest2 ) from vg a. 3: inputs ?i? ( atest2 ) and ?q? ( atest1 ) to adc. 4: outputs ?i? ( atest1 ) and ?q? ( atest2 ) from lpf. 5: inputs ?i? ( atest2 ) and ?q? ( atest1 ) to txmix. 6: outputs ?p? ( atest1 ) and ?n? ( atest2 ) fr om pr escaler . must be terminated externally . 7: connects tx if to rx if and simultaneously the atest1 pin to the internal vc node (see vc_in_test_en ). 8. connect atest1 (input) to atest2 (output) through single2diff and diff2single buffers, used for measurements on the test-interface reserved (0x30) - reserv e d register cont aining spare control and status bits bit field name reset r/w description 1 5 : 0 r e s [ 1 5 : 0 ] 0 r / w reserved for future use txfifo (0x3e) ? transmit fifo by te register bit field name reset r/w description 7 : 0 t x f i f o [ 7 : 0 ] - w transmit fifo by te register, w r ite only . reading the txfifo is only possible using ram read. note that the cry s tal oscillator must be running for w r iting to the txfifo. rxfifo (0x3f) ? receiv e fifo by te register bit field name reset r/w description 7 : 0 r x f i f o [ 7 : 0 ] - r / w receive fifo by te register, read / w r ite. note that the cry s tal oscillator must be running for accessing the rxfifo . chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 78 of 85
smartrf ? CC2420 test output signals the two digital output pins sfd and cca, can be set up to output test signals defined by iocfg1.sfdmux and iocfg1.ccamux . this is summarized in table 12 and table 13 below. sfdmux signal output on sfd pin description 0 sfd normal operation 1 adc_q[0] adc, q-branch, lsb used for random number generation 2 demod_resy nc_late high one 16 mhz cl ock cy cle each time the demodulator resy nchronises late 3 lock_status lock status, same as fsctrl.lock_status 4 mod_chipclk chip rate cl ock signal during transmission 5 mod_serial_clk bit rate cl ock signal during transmission 6 f f c t r l _ f s _ p d frequency sy nthesiz er pow er dow n, active high 7 ffctrl_adc_pd adc pow er dow n, active high 8 ffctrl_vga_pd vga pow er dow n, active high 9 ffctrl_rxbpf_pd receiver bandpass filter pow er dow n, active high 10 ffctrl_lnamix_pd receiver lna / mixer pow er dow n, active high 11 ffctrl_pa_p_pd pow e r amplifier pow er dow n, active high 12 agc_update high one 16 mhz clock cy cl e each time the agc updates its gain setting 13 vga_peak_det[1] vga peak detector, gain stage 1 14 vga_peak_det[3] vga peak detector, gain stage 3 15 agc_lnamix_gainmode[1] rf receiver frontend gain mode, bit 1 16 agc_vga_gain[1] vga gain setting, bit 1 1 7 v g a _ r e s e t _ n vga peakdetector reset signa, active low . 1 8 - r e s e r v e d 1 9 - r e s e r v e d 2 0 - r e s e r v e d 2 1 - r e s e r v e d 2 2 - r e s e r v e d 23 clk_8m 8 mhz clock signal output 24 xo sc16m_st able 16 mhz cr y s tal oscillator stab ilised, same as the status bit in t able 5 2 5 f s d i g _ f r e f frequency sy nthesiz er, 4 mhz reference signal 2 6 f s d i g _ f p l l frequency sy nthes izer, 4 mhz divided signal 2 7 f s d i g _ l o c k _ w i n d o w frequency sy nthesizer, lock w i ndow 28 window_sy n c frequency sy nthesizer, sy nchronized lock w i ndow 29 clk_adc adc clock signal 1 3 0 z e r o low 3 1 o n e h i g h table 12. sfd test signal select table chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 79 of 85
smartrf ? CC2420 ccamux signal output on cca pin description 0 c c a n o r m a l o p e r a t i o n 1 adc_i[0] adc, i-branch, lsb used for random number generation 2 demod_resy nch_early high one 16 mhz clock cy cle each time the demodulator resy nchronises early 3 lock_status lock status, same as fsctrl.lock_status 4 mod_chip chip rate dat a signal during transmission 5 m o d _ s e r i a l _ d a t a _ o u t bit rate data signal during transmission 6 f f c t r l _ f s _ p d frequency sy nthesiz er pow er dow n, active high 7 ffctrl_adc_pd adc pow er dow n, active high 8 ffctrl_vga_pd vga pow er dow n, active high 9 ffctrl_rxbpf_pd receiver bandpass filter pow er dow n, active high 10 ffctrl_lnamix_pd receiver lna / mixer pow er dow n, active high 11 ffctrl_pa_p_pd pow e r amplifier pow er dow n, active high 12 vga_peak_det[0] vga peak detector, gain stage 0 13 vga_peak_det[2] vga peak detector, gain stage 2 14 vga_peak_det[4] vga peak detector, gain stage 4 15 agc_lnamix_gainmode[0] rf receiver frontend gain mode, bit 0 16 agc_vga_gain[0] vga gain setting, bit 0 1 7 r x b p f _ c a l _ c l k receiver bandpa ss filter calibration clock 1 8 - r e s e r v e d 1 9 - r e s e r v e d 2 0 - r e s e r v e d 2 1 - r e s e r v e d 2 2 - r e s e r v e d 2 3 - r e s e r v e d 24 pd_f_comp frequency sy nthesizer frequency comparator value 2 5 f s d i g _ f r e f frequency sy nthesiz er, 4 mhz reference signal 2 6 f s d i g _ f p l l frequency sy nthes izer, 4 mhz divided signal 2 7 f s d i g _ l o c k _ w i n d o w frequency sy nthesizer, lock w i ndow 28 window_sy n c frequency sy nthesizer, sy nchronized lock w i ndow 29 clk_adc_dig adc clock signal 2 3 0 z e r o low 3 1 o n e h i g h table 13. cca test signal select table chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 80 of 85
smartrf ? CC2420 package description (qlp 48) note: the figure is an illustration only and not to scale. quad leadless package (qlp) d d 1 e e 1 e b l d 2 e 2 qlp 48 min max 6.9 7.0 7.1 6.65 6.75 6.85 6.9 7.0 7.1 6.65 6.75 6.85 0.5 0.18 0.30 0.3 0.4 0.5 5.05 5.10 5.15 5.05 5.10 5.15 all dimensions in mm the package is compliant to jedec standard mo-220. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 81 of 85
smartrf ? CC2420 package thermal properties thermal resistance air velocity [m/s] 0 rth,j-a [k/w] 25.6 soldering information recommended soldering profile is accordi ng to ipc/jedec j-std-020b, july 2002. plastic tube specification qlp 7x 7 mm antistatic tube. tube specification package tube width tube height tube length units per tube qlp 48 8.5 0.2 mm 2.2 +0.2/-0.1 mm 315 1.25 mm 43 carrier tape and reel specification carrier tape and reel is in accordance with eia specification 481. tape and reel specification p a c k a g e t a p e w i d t h c o m p o n e n t pitch hole pitch reel diameter units per reel qlp 48 16 mm 12 mm 4 mm 13 inch 4000 chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 82 of 85
smartrf ? CC2420 ordering information ordering part number description moq CC2420 single chip rf transceiver 43 (tube) CC2420/t&r single chip rf transceiver 4000 (tape and reel) CC2420dk cc24 2 0 development kit 1 CC2420dbk cc24 2 0 demonstration board kit 1 CC2420sk cc24 2 0 sample kit (5 pcs) 1 moq = minimum order quantity chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 83 of 85
smartrf ? CC2420 general information product status definitions data sheet identification product status definition advance information planned or under development this data sheet contains t he design specifications for product development. specif ications may change in any manner w i thout notice. preliminary e n g i n e e r i n g s a m p l e s and first production this data sheet contains preliminary data, and supplementary data w ill be published at a later date. chipcon reserves the right to make changes at any time w i thout notice in order to improve design and supply the best possible product. no identification noted full production this dat a sheet contains the final specifications. chipcon reserves the right to make changes at any time w i thout notice in order to improve design and supply the best possible product. obsolete not in production this data sheet contains specific ations on a product that has been discontinued by chipcon. the data sheet is printed for reference information only . disclaimer chipcon as believes the information contained herein is correct and accurate at the time of this printing. how e ver, chipcon as reserves the right to make changes to this product w i thout notice. chipcon as does not assume any responsibility for the use of the described product.; neither does it convey any license under its patent rights, or the rights of others. the latest updates are available at t he chipcon w ebsite or by contacting chipcon directly . as far as possible, major changes of pr oduct specifications and functionality , w ill be stated in product specific errata notes published at the chipcon w ebsite. customers are enc ouraged to sign up to the developers new s letter for the most recent updates on products and support tools. when a product is discontinued this w ill be done accordi ng to chipcon?s procedure for obsolete products as described in chipcon?s quality manual. this includes informing about last-tim e-buy options. the quality manual can be dow nloaded from chipcon?s w ebsite. trademarks sm artrf ? is a registered trademark of chipcon as. smartrf ? is chipcon's rf technology platform w i th rf library cells, modules and design ex pertise. based on smartrf ? technology chipcon develops standard component rf circuits as w e ll as full custom asics based on customer requirements and this technology . all other trademarks, registered trademarks and product names are the sole property of their respective ow ners. life support policy this chipcon product is not designed fo r use in life support appliances, devices , or other sy stems w here malfunction can reasonably be expected to result in si gnificant personal injury to the user, or as a critical component in any life support device or sy stem w hose failure to perform can be reasonably expected to cause the failure of the life support device or sy stem, or to affect its safety or effectivene ss. chipcon as customers using or selling these products for use in such applications do so at their ow n risk and agree to fully indemnify chipcon as for any damages resulting from any improper use or sale. ? 2003, chipcon as. all rights reserved. chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 84 of 85
smartrf ? CC2420 address information web s i te: http://www.chipcon.com e-mail: wireless@chipcon. com technical support email: support@chipcon.com technical support hotline: +47 22 95 85 45 headquarters: chipcon as gaustadallen 21 no-0349 oslo norway tel: +47 22 95 85 44 fax: +47 22 95 85 46 e- mail: wireless@chipcon. com us offices: chipcon inc., western us sales office 19925 stevens creek blvd. cupertino, ca 95014-2358 usa tel: +1 408 973 7845 fax: +1 408 973 7257 email: ussales@chipcon.com chipcon inc., easter n us sales o ffice 35 pinehurst avenue nashua, new hampshire, 03062 usa tel: +1 603 888 1326 fax: +1 603 888 4239 email: eastussales@chipcon.com sales office germany : chipcon as riedberghof 3 d-74379 ingersheim ge rma n y tel: +49 7142 9156815 fax: +49 7142 9156818 email: g e r m any sales@chipcon.com sales office a s ia : chipcon asia pasific 37f, asem tow e r 159-1 samsung-dong, kangnam-ku seoul 135-798 korea tel: +82 2 6001 3888 fax: +82 2 6001 3711 email: asiasales@chipcon.com chipcon as is an iso 9001:2000 certified company chipcon as sm artrf ? CC2420 preliminary datasheet (rev 1.0), 2003-11-17 page 85 of 85

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